[PATCH V12 3/4] arm64: dts: qcom: Add support for ipq9574 SoC and RDP433 variant
Devi Priya
quic_devipriy at quicinc.com
Fri Apr 14 03:01:59 PDT 2023
On 4/13/2023 2:16 AM, Konrad Dybcio wrote:
>
>
> On 10.04.2023 15:59, Devi Priya wrote:
>> Add initial device tree support for Qualcomm IPQ9574 SoC and
>> Reference Design Platform(RDP) 433 which is based on IPQ9574
>> family of SoCs
>>
>> Co-developed-by: Anusha Rao <quic_anusha at quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha at quicinc.com>
>> Co-developed-by: Poovendhan Selvaraj <quic_poovendh at quicinc.com>
>> Signed-off-by: Poovendhan Selvaraj <quic_poovendh at quicinc.com>
>> Signed-off-by: Devi Priya <quic_devipriy at quicinc.com>
>> ---
>
>> + soc: soc at 0 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0 0xffffffff>;
> this is equal to:
>
> ranges;
Konrad, on updating (ranges = <0 0 0 0xffffffff>; --> ranges;)
we see the below warnings:
arch/arm64/boot/dts/qcom/ipq9574.dtsi:103.3-10: Warning (ranges_format):
/soc at 0:ranges: empty "ranges" property but its #address-cells (1)
differs from / (2)
arch/arm64/boot/dts/qcom/ipq9574.dtsi:103.3-10: Warning (ranges_format):
/soc at 0:ranges: empty "ranges" property but its #size-cells (1) differs
from / (2)
Looks like, empty ranges property isn't supported if the parent and
child address spaces are non-identical.
Would you suggest to retain the ranges as such?
(ranges = <0 0 0 0xffffffff>;)
Thanks,
Devi Priya
>
> Could you fix that up when applying, Bjorn, should there be
> no other issues?
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio at linaro.org>
>
Thank you!
> Konrad
>
>> +
>> + tlmm: pinctrl at 1000000 {
>> + compatible = "qcom,ipq9574-tlmm";
>> + reg = <0x01000000 0x300000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 65>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + uart2_pins: uart2-state {
>> + pins = "gpio34", "gpio35";
>> + function = "blsp2_uart";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> + };
>> +
>> + gcc: clock-controller at 1800000 {
>> + compatible = "qcom,ipq9574-gcc";
>> + reg = <0x01800000 0x80000>;
>> + clocks = <&xo_board_clk>,
>> + <&sleep_clk>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + sdhc_1: mmc at 7804000 {
>> + compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
>> + reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
>> + reg-names = "hc", "cqhci";
>> +
>> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hc_irq", "pwr_irq";
>> +
>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>> + <&gcc GCC_SDCC1_APPS_CLK>,
>> + <&xo_board_clk>;
>> + clock-names = "iface", "core", "xo";
>> + non-removable;
>> + status = "disabled";
>> + };
>> +
>> + blsp1_uart2: serial at 78b1000 {
>> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> + reg = <0x078b1000 0x200>;
>> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>> + <&gcc GCC_BLSP1_AHB_CLK>;
>> + clock-names = "core", "iface";
>> + status = "disabled";
>> + };
>> +
>> + intc: interrupt-controller at b000000 {
>> + compatible = "qcom,msm-qgic2";
>> + reg = <0x0b000000 0x1000>, /* GICD */
>> + <0x0b002000 0x2000>, /* GICC */
>> + <0x0b001000 0x1000>, /* GICH */
>> + <0x0b004000 0x2000>; /* GICV */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + ranges = <0 0x0b00c000 0x3000>;
>> +
>> + v2m0: v2m at 0 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00000000 0xffd>;
>> + msi-controller;
>> + };
>> +
>> + v2m1: v2m at 1000 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00001000 0xffd>;
>> + msi-controller;
>> + };
>> +
>> + v2m2: v2m at 2000 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00002000 0xffd>;
>> + msi-controller;
>> + };
>> + };
>> +
>> + timer at b120000 {
>> + compatible = "arm,armv7-timer-mem";
>> + reg = <0x0b120000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + frame at b120000 {
>> + reg = <0x0b121000 0x1000>,
>> + <0x0b122000 0x1000>;
>> + frame-number = <0>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + frame at b123000 {
>> + reg = <0x0b123000 0x1000>;
>> + frame-number = <1>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame at b124000 {
>> + reg = <0x0b124000 0x1000>;
>> + frame-number = <2>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame at b125000 {
>> + reg = <0x0b125000 0x1000>;
>> + frame-number = <3>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame at b126000 {
>> + reg = <0x0b126000 0x1000>;
>> + frame-number = <4>;
>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame at b127000 {
>> + reg = <0x0b127000 0x1000>;
>> + frame-number = <5>;
>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame at b128000 {
>> + reg = <0x0b128000 0x1000>;
>> + frame-number = <6>;
>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> + };
>> +};
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