[RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its domain as parent

[gregkh at linuxfoundation.org]

On Fri, Oct 14, 2022 at 12:13:45PM +0000, Radovanovic, Aleksandar wrote:
> [AMD Official Use Only - General]
> 
> 
> 
> > -----Original Message-----
> > From: gregkh at linuxfoundation.org <gregkh at linuxfoundation.org>
> > Sent: 14 October 2022 12:55
> > To: Radovanovic, Aleksandar <aleksandar.radovanovic at amd.com>
> > Cc: Jason Gunthorpe <jgg at ziepe.ca>; Gupta, Nipun
> > <Nipun.Gupta at amd.com>; Marc Zyngier <maz at kernel.org>; Robin Murphy
> > <robin.murphy at arm.com>; robh+dt at kernel.org;
> > krzysztof.kozlowski+dt at linaro.org; rafael at kernel.org;
> > eric.auger at redhat.com; alex.williamson at redhat.com; cohuck at redhat.com;
> > Gupta, Puneet (DCG-ENG) <puneet.gupta at amd.com>;
> > song.bao.hua at hisilicon.com; mchehab+huawei at kernel.org;
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> > Anand, Harpreet <harpreet.anand at amd.com>; Agarwal, Nikhil
> > <nikhil.agarwal at amd.com>; Simek, Michal <michal.simek at amd.com>; git
> > (AMD-Xilinx) <git at amd.com>
> > Subject: Re: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its
> > domain as parent
> > 
> > Caution: This message originated from an External Source. Use proper
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> > 
> > 
> > On Fri, Oct 14, 2022 at 11:18:36AM +0000, Radovanovic, Aleksandar wrote:
> > > Anyway, I think we're straying off topic here, none of this is visible to the
> > kernel anyway. The question that we still need to answer is, are you OK with
> > the limitations I listed originally?
> > 
> > What original limitations?  
> 
> Limitations with regards to MSI message configuration of a CDX device:
> 
> 1) MSI write value is at most 16 useable bits
> 
> 2) MSI address value must be the same across all vectors of a single CDX device
> This would be the (potentially IOMMU translated) I/O address of
> GITS_TRANSLATER. As long as that IOMMU translation is consistent across a 
> single device, I think we should be OK.

It's been a while since I read the PCI spec, but this feels like it does
not follow what MSI is supposed to allow.  Is the "CDX" spec anywhere
that mentions any of this as to what is supposed to be allowed and
supported?

And what is a "single device" here in how the kernel knows about it?  Is
it a PCI device, or some other new structure that is handed to the
kernel from the BIOS?

thanks,

greg k-h