[PATCH v5 net-next 3/3] net: axienet: set mdio clock according to bus-frequency

[Andrew Lunn]

On Thu, Nov 17, 2022 at 11:40:14PM +0800, Andy Chiu wrote:
> Some FPGA platforms have 80KHz MDIO bus frequency constraint when
> connecting Ethernet to its on-board external Marvell PHY. Thus, we may
> have to set MDIO clock according to the DT. Otherwise, use the default
> 2.5 MHz, as specified by 802.3, if the entry is not present.
> 
> Also, change MAX_MDIO_FREQ to DEFAULT_MDIO_FREQ because we may actually
> set MDIO bus frequency higher than 2.5MHz if undelying devices support
> it. And properly disable the mdio bus clock in error path.
> 
> Signed-off-by: Andy Chiu <andy.chiu at sifive.com>

Reviewed-by: Andrew Lunn <andrew at lunn.ch>

    Andrew