LDREX and STREX in heterogeneous system？

[Catalin Marinas]

On Wed, Nov 09, 2022 at 04:34:13PM +0800, richard clark wrote:
> Suppose in a heterogeneous system, there're cortex-M7 and cortex-A72
> sharing the same bus. Does the below code sequence work as (ldr/str)ex
> expected?
> 
> r2 point to a uncached shared memory between M7 and A72
> 
> M7                                      A72
> ldrex r1, [r2]
>       ------------------------->  strex r0, r1, [r2]

In general, it won't. The exclusives are supposed to work in the same
inner shareable domain, so it depends on how the SoC has the M7 and A72
wired up. Are they cache coherent with each-other? Is there a global
exclusive monitor? The M7 may also need the MPU regions set up with the
Shareable attribute.

-- 
Catalin