LDREX and STREX in heterogeneous system？

[richard clark]

Hi Catalin and Mark,

Suppose in a heterogeneous system, there're cortex-M7 and cortex-A72
sharing the same bus. Does the below code sequence work as (ldr/str)ex
expected?

r2 point to a uncached shared memory between M7 and A72

M7                                      A72
ldrex r1, [r2]
      ------------------------->  strex r0, r1, [r2]

Richard