[PATCH 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations

[Rob Herring]

On Thu, Nov 3, 2022 at 3:29 AM Alexander Stein
<alexander.stein at ew.tq-group.com> wrote:
>
> Hi Marek,
>
> Am Mittwoch, 2. November 2022, 22:57:28 CET schrieb Marek Vasut:
> > The i.MX SoCs have various power domain configurations routed into
> > the PCIe IP. MX6SX is the only one which contains 2 domains and also
> > uses power-domain-names. MX6QDL do not use any domains. All the rest
> > uses one domain and does not use power-domain-names anymore.
> >
> > Document all those configurations in the DT binding document.
> >
> > Signed-off-by: Marek Vasut <marex at denx.de>
> > ---
> > Cc: Fabio Estevam <festevam at gmail.com>
> > Cc: Lucas Stach <l.stach at pengutronix.de>
> > Cc: Richard Zhu <hongxing.zhu at nxp.com>
> > Cc: Rob Herring <robh+dt at kernel.org>
> > Cc: Shawn Guo <shawnguo at kernel.org>
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: NXP Linux Team <linux-imx at nxp.com>
> > To: devicetree at vger.kernel.org
> > ---
> >  .../bindings/pci/fsl,imx6q-pcie.yaml          | 47 ++++++++++++++-----
> >  1 file changed, 34 insertions(+), 13 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index
> > 1cfea8ca72576..fc8d4d7b80b38 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -68,19 +68,6 @@ properties:
> >      description: A phandle to an fsl,imx7d-pcie-phy node. Additional
> >        required properties for imx7d-pcie and imx8mq-pcie.
> >
> > -  power-domains:
> > -    items:
> > -      - description: The phandle pointing to the DISPLAY domain for
> > -          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
> > -          imx8mq-pcie.
> > -      - description: The phandle pointing to the PCIE_PHY power domains
> > -          for imx6sx-pcie.
> > -
> > -  power-domain-names:
> > -    items:
> > -      - const: pcie
> > -      - const: pcie_phy
> > -
> >    resets:
> >      maxItems: 3
> >      description: Phandles to PCIe-related reset lines exposed by SRC
> > @@ -241,6 +228,40 @@ allOf:
> >                  - const: pcie_bus
> >                  - const: pcie_phy
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: fsl,imx6sx-pcie
> > +    then:
> > +      properties:
> > +        power-domains:
> > +          items:
> > +            - description: The phandle pointing to the DISPLAY domain for
> > +                imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
> > +                imx8mq-pcie.
> > +            - description: The phandle pointing to the PCIE_PHY power
> > domains +                for imx6sx-pcie.
> > +        power-domain-names:
> > +          items:
> > +            - const: pcie
> > +            - const: pcie_phy
> > +    else:
> > +      if:
> > +        not:
> > +          properties:
> > +            compatible:
> > +              contains:
> > +                enum:
> > +                  - fsl,imx6q-pcie
> > +                  - fsl,imx6qp-pcie
> > +      then:
> > +        properties:
> > +          power-domains:
> > +            description: |
> > +               The phandle pointing to the DISPLAY domain for imx6sx-pcie,
> > to +               PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. +
>
> Doesn't it makes more sense to keep the power-domains descriptions in the
> common part on top, as before, but adjust minItems/maxItems for each
> compatible?

Yes. Keep properties defined at the top level.

Rob