(EXT) [PATCH v3 7/7] arm64: dts: imx8mp: add GPU nodes

[Alexander Stein]

Am Montag, 28. Februar 2022, 21:17:31 CET schrieb Lucas Stach:
> Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP.
> 
> etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204
> etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341
> [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0
> 
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> Reviewed-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 31 +++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 9f2c335cc7a1..3ded7314c473 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -980,6 +980,37 @@ hsio_blk_ctrl: blk-ctrl at 32f10000 {
>  			};
>  		};
> 
> +		gpu3d: gpu at 38000000 {
> +			compatible = "vivante,gc";
> +			reg = <0x38000000 0x8000>;
> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
> +				 <&clk 
IMX8MP_CLK_GPU3D_SHADER_CORE>,
> +				 <&clk IMX8MP_CLK_GPU_ROOT>,
> +				 <&clk IMX8MP_CLK_GPU_AHB>;
> +			clock-names = "core", "shader", "bus", "reg";
> +			assigned-clocks = <&clk 
IMX8MP_CLK_GPU3D_CORE>,
> +					  <&clk 
IMX8MP_CLK_GPU3D_SHADER_CORE>;
> +			assigned-clock-parents = <&clk 
IMX8MP_SYS_PLL1_800M>,
> +						 <&clk 
IMX8MP_SYS_PLL1_800M>;
> +			assigned-clock-rates = <800000000>, 
<800000000>;
> +			power-domains = <&pgc_gpu3d>;
> +		};
> +
> +		gpu2d: gpu at 38008000 {
> +			compatible = "vivante,gc";
> +			reg = <0x38008000 0x8000>;
> +			interrupts = <GIC_SPI 25 
IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
> +				 <&clk IMX8MP_CLK_GPU_ROOT>,
> +				 <&clk IMX8MP_CLK_GPU_AHB>;
> +			clock-names = "core", "bus", "reg";
> +			assigned-clocks = <&clk 
IMX8MP_CLK_GPU2D_CORE>;
> +			assigned-clock-parents = <&clk 
IMX8MP_SYS_PLL1_800M>;
> +			assigned-clock-rates = <800000000>;
> +			power-domains = <&pgc_gpu2d>;
> +		};
> +
>  		gic: interrupt-controller at 38800000 {
>  			compatible = "arm,gic-v3";
>  			reg = <0x38800000 0x10000>,


Tested-by: Alexander Stein <alexander.stein at ew.tq-group.com>