[PATCH v1 3/4] arm64/mte: Add hwcap for asymmetric mode

[Catalin Marinas]

On Thu, Jan 27, 2022 at 07:57:11PM +0000, Mark Brown wrote:
> diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
> index b72ff17d600a..a8f30963e550 100644
> --- a/Documentation/arm64/elf_hwcaps.rst
> +++ b/Documentation/arm64/elf_hwcaps.rst
> @@ -259,6 +259,11 @@ HWCAP2_RPRES
>  
>      Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
>  
> +HWCAP2_MTE3
> +
> +    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described
> +    by Documentation/arm64/memory-tagging-extension.rst.

In hindsight, we should have called the other HWCAP2_MTE2 but since we
decided not to expose MTE == 0b0001 to user, we removed the '2'. Anyway,
I'm fine with HWCAP2_MTE3.

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>