[PATCH net v3 0/9] Xilinx axienet fixes

[Radhey Shyam Pandey]

> -----Original Message-----
> From: Robert Hancock <robert.hancock at calian.com>
> Sent: Wednesday, January 19, 2022 4:35 AM
> To: netdev at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org; davem at davemloft.net;
> kuba at kernel.org; Michal Simek <michals at xilinx.com>; Radhey Shyam Pandey
> <radheys at xilinx.com>; daniel at iogearbox.net; andrew at lunn.ch
> Subject: Re: [PATCH net v3 0/9] Xilinx axienet fixes
> 
> On Tue, 2022-01-18 at 15:41 -0600, Robert Hancock wrote:
> > Various fixes for the Xilinx AXI Ethernet driver.
> >
> > Changed since v2:
> > -added Reviewed-by tags, added some explanation to commit messages, no
> > code changes
> >
> > Changed since v1:
> > -corrected a Fixes tag to point to mainline commit -split up reset
> > changes into 3 patches -added ratelimit on netdev_warn in TX busy case
> >
> > Robert Hancock (9):
> >   net: axienet: increase reset timeout
> >   net: axienet: Wait for PhyRstCmplt after core reset
> >   net: axienet: reset core on initialization prior to MDIO access
> >   net: axienet: add missing memory barriers
> >   net: axienet: limit minimum TX ring size
> >   net: axienet: Fix TX ring slot available check
> >   net: axienet: fix number of TX ring slots for available check
> >   net: axienet: fix for TX busy handling
> >   net: axienet: increase default TX ring size to 128
> >
> >  .../net/ethernet/xilinx/xilinx_axienet_main.c | 135
> > +++++++++++-------
> >  1 file changed, 84 insertions(+), 51 deletions(-)
> >
> 
> FYI, for the netdev/cc_maintainers Patchwork check, I dropped Ariane Keller <
> ariane.keller at tik.ee.ethz.ch> from the CC list as their mail was bouncing.

Thanks for the series. I have added Harini to this thread to also review
and add her Tested-by tag. Just FYI- We are in feature freeze so plan is
to close on this series by next week. Hope that's fine.

> 
> --
> Robert Hancock
> Senior Hardware Designer, Calian Advanced Technologies www.calian.com