[PATCH net v3 0/9] Xilinx axienet fixes

[Robert Hancock]

On Tue, 2022-01-18 at 15:41 -0600, Robert Hancock wrote:
> Various fixes for the Xilinx AXI Ethernet driver.
> 
> Changed since v2:
> -added Reviewed-by tags, added some explanation to commit
> messages, no code changes
> 
> Changed since v1:
> -corrected a Fixes tag to point to mainline commit
> -split up reset changes into 3 patches
> -added ratelimit on netdev_warn in TX busy case
> 
> Robert Hancock (9):
>   net: axienet: increase reset timeout
>   net: axienet: Wait for PhyRstCmplt after core reset
>   net: axienet: reset core on initialization prior to MDIO access
>   net: axienet: add missing memory barriers
>   net: axienet: limit minimum TX ring size
>   net: axienet: Fix TX ring slot available check
>   net: axienet: fix number of TX ring slots for available check
>   net: axienet: fix for TX busy handling
>   net: axienet: increase default TX ring size to 128
> 
>  .../net/ethernet/xilinx/xilinx_axienet_main.c | 135 +++++++++++-------
>  1 file changed, 84 insertions(+), 51 deletions(-)
> 

FYI, for the netdev/cc_maintainers Patchwork check, I dropped Ariane Keller <
ariane.keller at tik.ee.ethz.ch> from the CC list as their mail was bouncing.

-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com