[PATCH v2 00/38] arm64/sysreg: Convert aarch32 id regs
Will Deacon
will at kernel.org
Fri Dec 2 03:17:42 PST 2022
[+Marc]
On Wed, 30 Nov 2022 17:15:59 +0000, James Morse wrote:
> Changes since the v1
> * Duplicate definition muck up in patch 29 fixed.
> * Rebased onto arm64/for-next/sysregs, which is just rc4.
>
Applied to arm64 (for-next/sysregs), thanks!
Note that this conflicts with Marc's PMU rework in the kvmarm tree in
slightly annoying ways (things like "IMP_DEF" => "IMPDEF"). I've had a
crack at resolving that at the end of this email.
[01/38] arm64/sysreg: Standardise naming for ID_MMFR0_EL1
https://git.kernel.org/arm64/c/37622bae3db3
[02/38] arm64/sysreg: Standardise naming for ID_MMFR4_EL1
https://git.kernel.org/arm64/c/5ea1534ec320
[03/38] arm64/sysreg: Standardise naming for ID_MMFR5_EL1
https://git.kernel.org/arm64/c/7b24177c631d
[04/38] arm64/sysreg: Standardise naming for ID_ISAR0_EL1
https://git.kernel.org/arm64/c/52b3dc559a4c
[05/38] arm64/sysreg: Standardise naming for ID_ISAR4_EL1
https://git.kernel.org/arm64/c/3f08e378f00e
[06/38] arm64/sysreg: Standardise naming for ID_ISAR5_EL1
https://git.kernel.org/arm64/c/816c8638d8c6
[07/38] arm64/sysreg: Standardise naming for ID_ISAR6_EL1
https://git.kernel.org/arm64/c/eef4344f779f
[08/38] arm64/sysreg: Standardise naming for ID_PFR0_EL1
https://git.kernel.org/arm64/c/e0bf98fef3fd
[09/38] arm64/sysreg: Standardise naming for ID_PFR1_EL1
https://git.kernel.org/arm64/c/0a648056d68d
[10/38] arm64/sysreg: Standardise naming for ID_PFR2_EL1
https://git.kernel.org/arm64/c/1ecf3dcb1363
[11/38] arm64/sysreg: Standardise naming for ID_DFR0_EL1
https://git.kernel.org/arm64/c/f4f5969e3542
[12/38] arm64/sysreg: Standardise naming for ID_DFR1_EL1
https://git.kernel.org/arm64/c/d092106d7353
[13/38] arm64/sysreg: Standardise naming for MVFR0_EL1
https://git.kernel.org/arm64/c/a3aab94801de
[14/38] arm64/sysreg: Standardise naming for MVFR1_EL1
https://git.kernel.org/arm64/c/d3e1aa85b1b2
[15/38] arm64/sysreg: Standardise naming for MVFR2_EL1
https://git.kernel.org/arm64/c/c6e155e8e561
[16/38] arm64/sysreg: Extend the maximum width of a register and symbol name
https://git.kernel.org/arm64/c/7587cdef5592
[17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation
https://git.kernel.org/arm64/c/8893df290e36
[18/38] arm64/sysreg: Convert ID_MMFR1_EL1 to automatic generation
https://git.kernel.org/arm64/c/7e2f00bea3db
[19/38] arm64/sysreg: Convert ID_MMFR2_EL1 to automatic generation
https://git.kernel.org/arm64/c/fbfba88b6ae1
[20/38] arm64/sysreg: Convert ID_MMFR3_EL1 to automatic generation
https://git.kernel.org/arm64/c/8fe2a9c578b0
[21/38] arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation
https://git.kernel.org/arm64/c/5b380ae0e2b3
[22/38] arm64/sysreg: Convert ID_ISAR0_EL1 to automatic generation
https://git.kernel.org/arm64/c/258a96b25a9d
[23/38] arm64/sysreg: Convert ID_ISAR1_EL1 to automatic generation
https://git.kernel.org/arm64/c/892386a6a807
[24/38] arm64/sysreg: Convert ID_ISAR2_EL1 to automatic generation
https://git.kernel.org/arm64/c/dfa70ae8d8c2
[25/38] arm64/sysreg: Convert ID_ISAR3_EL1 to automatic generation
https://git.kernel.org/arm64/c/d07016c96530
[26/38] arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation
https://git.kernel.org/arm64/c/849cc9bd9f0e
[27/38] arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation
https://git.kernel.org/arm64/c/f4e9ce12dd88
[28/38] arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation
https://git.kernel.org/arm64/c/5ea58a1b5c7a
[29/38] arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation
https://git.kernel.org/arm64/c/fb0b8d1a24d8
[30/38] arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation
https://git.kernel.org/arm64/c/1224308075f1
[31/38] arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation
https://git.kernel.org/arm64/c/039d372305ff
[32/38] arm64/sysreg: Convert MVFR0_EL1 to automatic generation
https://git.kernel.org/arm64/c/e79c94a2a487
[33/38] arm64/sysreg: Convert MVFR1_EL1 to automatic generation
https://git.kernel.org/arm64/c/c9b718eda706
[34/38] arm64/sysreg: Convert MVFR2_EL1 to automatic generation
https://git.kernel.org/arm64/c/f70a810e01b2
[35/38] arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generation
https://git.kernel.org/arm64/c/8a950efa1ff0
[36/38] arm64/sysreg: Convert ID_AFR0_EL1 to automatic generation
https://git.kernel.org/arm64/c/58e010516ee6
[37/38] arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation
https://git.kernel.org/arm64/c/d044a9fbace7
[38/38] arm64/sysreg: Convert ID_DFR1_EL1 to automatic generation
https://git.kernel.org/arm64/c/fa057722978e
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
--->8
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 528d253c571a..d5ee52d6bf73 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1071,9 +1071,9 @@ static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
static u8 perfmon_to_pmuver(u8 perfmon)
{
switch (perfmon) {
- case ID_DFR0_PERFMON_8_0:
+ case ID_DFR0_EL1_PerfMon_PMUv3:
return ID_AA64DFR0_EL1_PMUVer_IMP;
- case ID_DFR0_PERFMON_IMP_DEF:
+ case ID_DFR0_EL1_PerfMon_IMPDEF:
return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
default:
/* Anything ARMv8.1+ and NI have the same value. For now. */
@@ -1085,9 +1085,9 @@ static u8 pmuver_to_perfmon(u8 pmuver)
{
switch (pmuver) {
case ID_AA64DFR0_EL1_PMUVer_IMP:
- return ID_DFR0_PERFMON_8_0;
+ return ID_DFR0_EL1_PerfMon_PMUv3;
case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
- return ID_DFR0_PERFMON_IMP_DEF;
+ return ID_DFR0_EL1_PerfMon_IMPDEF;
default:
/* Anything ARMv8.1+ and NI have the same value. For now. */
return pmuver;
@@ -1151,8 +1151,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r
val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
break;
case SYS_ID_DFR0_EL1:
- val &= ~ARM64_FEATURE_MASK(ID_DFR0_PERFMON);
- val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_PERFMON),
+ val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
+ val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon),
pmuver_to_perfmon(vcpu_pmuver(vcpu)));
break;
}
@@ -1307,12 +1307,12 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
* AArch64 side (as everything is emulated with that), and
* that this is a PMUv3.
*/
- perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_PERFMON), val);
- if ((perfmon != ID_DFR0_PERFMON_IMP_DEF && perfmon > host_perfmon) ||
- (perfmon != 0 && perfmon < ID_DFR0_PERFMON_8_0))
+ perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val);
+ if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) ||
+ (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3))
return -EINVAL;
- valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_PERFMON_IMP_DEF);
+ valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_EL1_PerfMon_IMPDEF);
/* Make sure view register and PMU support do match */
if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
@@ -1320,7 +1320,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
/* We can only differ with PerfMon, and anything else is an error */
val ^= read_id_reg(vcpu, rd);
- val &= ~ARM64_FEATURE_MASK(ID_DFR0_PERFMON);
+ val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon);
if (val)
return -EINVAL;
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