[PATCH v2 00/38] arm64/sysreg: Convert aarch32 id regs

[Will Deacon]

Hi James,

On Wed, Nov 30, 2022 at 05:15:59PM +0000, James Morse wrote:
> Changes since the v1
>  * Duplicate definition muck up in patch 29 fixed.
>  * Rebased onto arm64/for-next/sysregs, which is just rc4.
> 
> ---
> 
> To cleanup an erratum affecting aarch32, I wanted a mask for an id register.
> This would have been quick to add, but the right thing to do is to convert
> that register to automatic generation. If I was going that far, I may as
> well do the lot...

So with this applied, we have a couple of duplicate definitions from
sysregs.h (ID_DFR1_EL1_MTPMU_SHIFT and GMID_EL1_BS_SHIFT). I think the
latter was probably even there before. We also have GMID_EL1_BS_SIZE
vs GMID_EL1_BS_WIDTH.

Mind if I clean that as a patch on top up as per below?

Will

--->8

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 3350fcdbde08..097488cee174 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -667,8 +667,6 @@
 #define ID_AA64MMFR0_EL1_PARANGE_MAX   ID_AA64MMFR0_EL1_PARANGE_48
 #endif
 
-#define ID_DFR1_EL1_MTPMU_SHIFT                0
-
 #if defined(CONFIG_ARM64_4K_PAGES)
 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT           ID_AA64MMFR0_EL1_TGRAN4_SHIFT
 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN   ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
@@ -719,10 +717,6 @@
 #define SYS_RGSR_EL1_SEED_SHIFT        8
 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL
 
-/* GMID_EL1 field definitions */
-#define GMID_EL1_BS_SHIFT      0
-#define GMID_EL1_BS_SIZE       4
-
 /* TFSR{,E0}_EL1 bit definitions */
 #define SYS_TFSR_EL1_TF0_SHIFT 0
 #define SYS_TFSR_EL1_TF1_SHIFT 1
diff --git a/arch/arm64/lib/mte.S b/arch/arm64/lib/mte.S
index 1b7c93ae7e63..5018ac03b6bf 100644
--- a/arch/arm64/lib/mte.S
+++ b/arch/arm64/lib/mte.S
@@ -18,7 +18,7 @@
  */
        .macro  multitag_transfer_size, reg, tmp
        mrs_s   \reg, SYS_GMID_EL1
-       ubfx    \reg, \reg, #GMID_EL1_BS_SHIFT, #GMID_EL1_BS_SIZE
+       ubfx    \reg, \reg, #GMID_EL1_BS_SHIFT, #GMID_EL1_BS_WIDTH
        mov     \tmp, #4
        lsl     \reg, \tmp, \reg
        .endm