[PATCH v3 0/9] add the imx8m pcie phy driver and imx8mm pcie support

[Richard Zhu]

<snipped...>
> 
> Richard,
> 
> What is this 'invalid resource' about? I see that with my downstream
> IMX8MM PCIe driver as well and have been asked about it.
> 
[Richard Zhu] Hi Tim:
This complain is caused by the following codes in pcie-designware.c driver.
I'm not sure that why there is only size assignment after the res valid check, and do nothing if the res is invalid.
It seems that it is an expected design logic refer to the later codes.
                if (!pci->atu_base) {
                        struct resource *res =
                                platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
                        if (res)
                                pci->atu_size = resource_size(res);
                        pci->atu_base = devm_ioremap_resource(dev, res);
                        if (IS_ERR(pci->atu_base))
                                pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
                }

Since the default offset is used on i.MX8MM, the "atu" is not specified in i.MX8MM PCIe DT node, so there is no real res at all.
Then, devm_ioremap_resource() would complain the invalid resource.

> > [    1.316305] imx6q-pcie 33800000.pcie: iATU unroll: enabled
> > [    1.321799] imx6q-pcie 33800000.pcie: Detected iATU regions: 4
> outbound, 4 inbound
> > [    1.429803] imx6q-pcie 33800000.pcie: Link up
> > [    1.534497] imx6q-pcie 33800000.pcie: Link up
> > [    1.538870] imx6q-pcie 33800000.pcie: Link up, Gen2
> > [    1.550364] imx6q-pcie 33800000.pcie: Link up
> > [    1.550487] imx6q-pcie 33800000.pcie: PCI host bridge to bus 0000:00
> > [    1.565545] pci_bus 0000:00: root bus resource [bus 00-ff]
> > [    1.573834] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
> > [    1.580055] pci_bus 0000:00: root bus resource [mem
> 0x18000000-0x1fefffff]
> > [    1.586968] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
> > [    1.592997] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
> > [    1.599282] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff
> pref]
> > [    1.606033] pci 0000:00:00.0: supports D1
> > [    1.610053] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
> D3cold
> > [    1.618206] pci 0000:01:00.0: [15b7:5002] type 00 class 0x010802
> > [    1.624293] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00003fff
> 64bit]
> > [    1.631177] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x000000ff
> 64bit]
> > [    1.638409] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth,
> limited by 5.0 GT/s PCIe x1 link at 0000:00:00.0 (capable of 31.504 Gb/s with
> 8.0 GT/s PCIe x4 link)
> > [    1.664931] pci 0000:00:00.0: BAR 0: assigned [mem
> 0x18000000-0x180fffff]
> > [    1.671745] pci 0000:00:00.0: BAR 14: assigned [mem
> 0x18100000-0x181fffff]
> > [    1.678634] pci 0000:00:00.0: BAR 6: assigned [mem
> 0x18200000-0x1820ffff pref]
> > [    1.685873] pci 0000:01:00.0: BAR 0: assigned [mem
> 0x18100000-0x18103fff 64bit]
> > [    1.693222] pci 0000:01:00.0: BAR 4: assigned [mem
> 0x18104000-0x181040ff 64bit]
> > [    1.700577] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> > [    1.705814] pci 0000:00:00.0:   bridge window [mem
> 0x18100000-0x181fffff]
> > [    1.712972] pcieport 0000:00:00.0: PME: Signaling with IRQ 216
> > "
> > Regarding the log you pasted, it seems that the clock is not feed to PHY
> properly.
> >
> > Anyway, let's waiting for the v4 series, then make a try. Thanks for your
> great help to make the double tests.
> >
> 
> My boards do not use CLKREQ# so I do not have that defined in pinmux and I
> found that if I add MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B PCIe
> works on my board but this isn't a solution just a work-around (I have boards
> that use the only two possible pins for CLKREQ as other features).
> 
> Similarly you will find on the imx8mm-evk if you comment out the CLKREQ
> (which isn't required) the imx8mmevk will end up hanging like my boards:
[Richard Zhu] Hi Tim:
Regarding the SPEC, the CLKREQ# is mandatory required, and should be configured as an open drain, active low signal.
And this signal should be driven low by the PCIe M.2 device to request the REF clock be available(active low).
So, there is such kind of CLKREQ# pin definition on i.MX8MM EVK board.

Anyway, I think the external OSC circuit should be always running if there is no CLKREQ# on your HW board design.

> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index 5ce43daa0c8b..f0023b48f475 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -448,7 +448,9 @@
> 
>         pinctrl_pcie0: pcie0grp {
>                 fsl,pins = <
> +/*
> 
> MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
> +*/
>                         MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21
> 0x41
>                 >;
>         };
> 
> I have PCIe working with a driver that I ported from NXP's kernel which differs
> from your driver in that the PCIe PHY is not abstracted to its own driver so I
> think this has something to do with the order in which the phy is reset or
> initialized? The configuration of gpr14 bits looks correct to me.
[Richard Zhu] The CLKREQ# PIN definition shouldn't be masked.
In the NXP's local BSP kernel, I just force CLKREQ# low to level up the HW compatibility.
That's might the reason why the PCIe works on your HW board although the CLKREQ# PIN is not defined.
This method is a little rude and violate the SPEC, and not recommended although it levels up the HW compatibility.
So I drop this method in this series.

BR
Richard
> 
> Best regards,
> 
> Tim