[PATCH v5 05/19] arm64: Add support for trace synchronization barrier

[Suzuki K Poulose]

On 23/03/2021 18:21, Catalin Marinas wrote:
> Hi Suzuki?
> 
> On Tue, Mar 23, 2021 at 12:06:33PM +0000, Suzuki K Poulose wrote:
>> tsb csync synchronizes the trace operation of instructions.
>> The instruction is a nop when FEAT_TRF is not implemented.
>>
>> Cc: Mathieu Poirier <mathieu.poirier at linaro.org>
>> Cc: Mike Leach <mike.leach at linaro.org>
>> Cc: Catalin Marinas <catalin.marinas at arm.com>
>> Cc: Will Deacon <will.deacon at arm.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose at arm.com>
> 
> How do you plan to merge these patches? If they go via the coresight
> tree:
> 

Ideally all of this should go via the CoreSight tree to have the 
dependencies solved at one place. But there are some issues :

If this makes to 5.13 queue for CoreSight,

1) CoreSight next is based on rc2 at the moment and we have fixes gone
into rc3 and later, which this series will depend on. (We could move
the next tree forward to a later rc to solve this).

2) There could be conflicts with the kvmarm tree for the KVM host 
changes (That has dependency on the TRBE definitions patch).

If it doesn't make to 5.13 queue, it would be good to have this patch, 
the TRBE defintions and the KVM host patches queued for 5.13 (not sure
if this is acceptable) and we could rebase the CoreSight changes on 5.13
and push it to next release.

I am open for other suggestions.

Marc, Mathieu,

Thoughts ?

> Acked-by: Catalin Marinas <catalin.marinas at arm.com>
> 

Thanks
Suzuki