[PATCH v5 05/19] arm64: Add support for trace synchronization barrier

[Catalin Marinas]

Hi Suzuki?

On Tue, Mar 23, 2021 at 12:06:33PM +0000, Suzuki K Poulose wrote:
> tsb csync synchronizes the trace operation of instructions.
> The instruction is a nop when FEAT_TRF is not implemented.
> 
> Cc: Mathieu Poirier <mathieu.poirier at linaro.org>
> Cc: Mike Leach <mike.leach at linaro.org>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose at arm.com>

How do you plan to merge these patches? If they go via the coresight
tree:

Acked-by: Catalin Marinas <catalin.marinas at arm.com>