[PATCH v2] ARM: dts: ixp4xx: Add Arcom Vulcan device tree

[Marc Zyngier]

On Wed, 28 Jul 2021 00:45:19 +0100,
Linus Walleij <linus.walleij at linaro.org> wrote:
> 
> On Tue, Jul 27, 2021 at 8:44 PM Marc Zyngier <maz at kernel.org> wrote:
> 
> > Thanks a lot for doing this. I'm slowly getting this box up and
> > running again, and noticed a couple of issues with the DT, see below.
> 
> Hey :)
> 
> Do you want me to do my best to fix it up or will you send me
> a patch on top I can just fold in to get it the way you want it?

Here's the state of my tree (everything else is just kernel config).
Just fold it into your current patch it you're happy with it.

I'll keep hacking at it when I have some spare time.

Thanks,

	M.

diff --git a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
index 16806deab559..f8a29a88f0c5 100644
--- a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
@@ -17,7 +17,6 @@ / {
 	#size-cells = <1>;
 
 	memory at 0 {
-		/* CHECKME: 64 MB SDRAM - based on dma zone in boardfile */
 		device_type = "memory";
 		reg = <0x00000000 0x4000000>;
 	};
@@ -44,7 +59,11 @@ flash at 0,0 {
 				bank-width = <2>;
 				/*
 				 * 32 MB of Flash in 0x20000 byte blocks
-				 * mapped in at CS0 and CS1
+				 * mapped in at CS0 and CS1.
+				 *
+				 * The documentation mentions the existence
+				 * of a 16MB version, which we conveniently
+				 * ignore. Shout if you own one!
 				 */
 				reg = <0 0x00000000 0x2000000>;
 
@@ -55,15 +74,14 @@ flash at 0,0 {
 
 				partitions {
 					compatible = "redboot-fis";
-					/* CHECKME: FIS eraseblock at 0x1fe0000? */
-					fis-index-block = <0xff>;
+					fis-index-block = <0x1ff>;
 				};
 			};
 			sram at 2,0 {
 				/* 256 KB SDRAM memory at CS2 */
 				compatible = "shared-dma-pool";
 				device_type = "memory";
-				reg = <1 0x00000000 0x40000>;
+				reg = <2 0x00000000 0x40000>;
 				no-map;
 				/* Expansion bus settings */
 				intel,ixp4xx-eb-t3 = <1>;
@@ -117,20 +135,18 @@ pci at c0000000 {
 			 *
 			 * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
 			 * per slot. This interrupt is shared (OR:ed) by all four pins.
-			 *
-			 * CHECKME: is the interrupt setup on Vulcan really this cheap?
 			 */
 			interrupt-map =
-			/* IDSEL 1 */
-			<0x0800 0 0 1 &gpio0 2 3>, /* INT A on slot 1 is irq 2 */
-			<0x0800 0 0 2 &gpio0 2 3>, /* INT B on slot 1 is irq 2 */
-			<0x0800 0 0 3 &gpio0 2 3>, /* INT C on slot 1 is irq 2 */
-			<0x0800 0 0 4 &gpio0 2 3>, /* INT D on slot 1 is irq 2 */
-			/* IDSEL 2 */
-			<0x1000 0 0 1 &gpio0 3 3>, /* INT A on slot 2 is irq 3 */
-			<0x1000 0 0 2 &gpio0 3 3>, /* INT B on slot 2 is irq 3 */
-			<0x1000 0 0 3 &gpio0 3 3>, /* INT C on slot 2 is irq 3 */
-			<0x1000 0 0 4 &gpio0 3 3>; /* INT D on slot 2 is irq 3 */
+			/* IDSEL 1, all INTx are mapped to irq 2 */
+			<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>,
+			<0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>,
+			<0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>,
+			<0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>,
+			/* IDSEL 2, all INTx are mapped to irq 3 */
+			<0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>,
+			<0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>,
+			<0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>,
+			<0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>;
 		};
 
 		/* EthB */


-- 
Without deviation from the norm, progress is not possible.