[PATCH] arm64: kernel: disable CNP on Carmel

[Catalin Marinas]

On Wed, Feb 17, 2021 at 10:43:52AM +0530, Anshuman Khandual wrote:
> On 2/17/21 7:01 AM, Rich Wiley wrote:
> > On NVIDIA Carmel cores, CNP behaves differently than it does on standard
> > ARM cores. On Carmel, if two cores have CNP enabled and share an L2 TLB
> > entry created by core0 for a specific ASID, a non-shareable TLBI from
> > core1 may still see the shared entry. On standard ARM cores, that TLBI
> > will invalidate the shared entry as well.
> 
> Could you please explain more on "may still see the shared entry" on the
> NVIDIA Carmel core vs "invalid the shared entry" on standard ARM core.

That's about the CnP feature where more than one core can share the same
TLB.

> > This causes issues with patchsets that attempt to do local TLBIs based
> 
> A new patchset ? Does it impact any existing functionality ? What sort of
> issues this create ?
> 
> > on cpumasks instead of broadcast TLBIs. Avoid these issues by disabling
> 
> Does it affect all existing local TLBI which iterate over cpumask or are
> there some particular situations ? The problem description here needs to
> be more clear and specific.

Local TLBI does not work as described in the ARM ARM w.r.t. CnP, so CnP
needs disabling.

-- 
Catalin