[PATCH] arm64: kernel: disable CNP on Carmel
anshuman.khandual at arm.com
Wed Feb 17 00:13:52 EST 2021
On 2/17/21 7:01 AM, Rich Wiley wrote:
> On NVIDIA Carmel cores, CNP behaves differently than it does on standard
> ARM cores. On Carmel, if two cores have CNP enabled and share an L2 TLB
> entry created by core0 for a specific ASID, a non-shareable TLBI from
> core1 may still see the shared entry. On standard ARM cores, that TLBI
> will invalidate the shared entry as well.
Could you please explain more on "may still see the shared entry" on the
NVIDIA Carmel core vs "invalid the shared entry" on standard ARM core.
> This causes issues with patchsets that attempt to do local TLBIs based
A new patchset ? Does it impact any existing functionality ? What sort of
issues this create ?
> on cpumasks instead of broadcast TLBIs. Avoid these issues by disabling
Does it affect all existing local TLBI which iterate over cpumask or are
there some particular situations ? The problem description here needs to
be more clear and specific.
> CNP support for NVIDIA Carmel cores.
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