[PATCH 15/18] irqchip/apple-aic: Add support for the Apple Interrupt Controller

[Arnd Bergmann]

On Mon, Feb 8, 2021 at 12:36 PM Marc Zyngier <maz at kernel.org> wrote:
>
> On Mon, 08 Feb 2021 10:29:23 +0000, Arnd Bergmann <arnd at kernel.org> wrote:
> >
> > On Mon, Feb 8, 2021 at 10:25 AM Marc Zyngier <maz at kernel.org> wrote:
> > > On Thu, 04 Feb 2021 20:39:48 +0000, Hector Martin <marcan at marcan.st> wrote:
> >
> > > > +{
> > > > +     return readl(ic->base + reg);
> > >
> > > Please consider using the _relaxed accessors, as I don't think any of
> > > these interacts with memory (apart from IPIs, of course).
> >
> > MSI interrupts require serializing with DMA, so at the minimum I think there
> > needs to be something that ensures that DMA from device into memory
> > has completed before delivering the completion interrupt to a driver. This
> > may already be implied when the AIC is entered, but this is hard to know
> > without actual hardware specs.
>
> If there is a sync with memory required, it should happen at the point
> where it is Acked, not when masked/unmasked or anything else. And
> given that you want to sync with an external agent (the DMA producer),
> the DMB generated by readl won't save you, as it only orders CPU
> accesses AFAICT.

If the dmb in readl() is not sufficient for preventing the speculative read
on DMA data from a device that sent the MSI, why is it sufficient for
the case in which any device driver relies on readl() from a device
register to ensure that DMA is complete?

I had expected those two cases to be equivalent.

> So if MSIs require some additional synchronisation we probably need a
> DSB somewhere if the HW doesn't guarantee ordering of DMA vs
> MSIs. Whether it does or not is anyone's bet.

Right, for all we know it could require a much more heavyweight barrier
as it does on certain broken SoCs, or nothing at all.

      Arnd