[PATCH] net: Fix comment errors
xiao33522 at qq.com
xiao33522 at qq.com
Fri Apr 9 10:21:49 BST 2021
From: xiaolinkui <xiaolinkui at kylinos.cn>
clk_scr_i should be clk_csr_i.
Signed-off-by: xiaolinkui <xiaolinkui at kylinos.cn>
---
include/linux/stmmac.h | 12 ++++++------
include/linux/sxgbe_platform.h | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index a302982de2d7..19e4344283df 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -28,12 +28,12 @@
* This could also be configured at run time using CPU freq framework. */
/* MDC Clock Selection define*/
-#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
-#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
-#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
-#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
-#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
-#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
+#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_csr_i/42 */
+#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_csr_i/62 */
+#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_csr_i/16 */
+#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_csr_i/26 */
+#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_csr_i/102 */
+#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_csr_i/122 */
/* MTL algorithms identifiers */
#define MTL_TX_ALGORITHM_WRR 0x0
diff --git a/include/linux/sxgbe_platform.h b/include/linux/sxgbe_platform.h
index 966146f7267a..d56bbd32e966 100644
--- a/include/linux/sxgbe_platform.h
+++ b/include/linux/sxgbe_platform.h
@@ -13,12 +13,12 @@
#include <linux/phy.h>
/* MDC Clock Selection define*/
-#define SXGBE_CSR_100_150M 0x0 /* MDC = clk_scr_i/62 */
-#define SXGBE_CSR_150_250M 0x1 /* MDC = clk_scr_i/102 */
-#define SXGBE_CSR_250_300M 0x2 /* MDC = clk_scr_i/122 */
-#define SXGBE_CSR_300_350M 0x3 /* MDC = clk_scr_i/142 */
-#define SXGBE_CSR_350_400M 0x4 /* MDC = clk_scr_i/162 */
-#define SXGBE_CSR_400_500M 0x5 /* MDC = clk_scr_i/202 */
+#define SXGBE_CSR_100_150M 0x0 /* MDC = clk_csr_i/62 */
+#define SXGBE_CSR_150_250M 0x1 /* MDC = clk_csr_i/102 */
+#define SXGBE_CSR_250_300M 0x2 /* MDC = clk_csr_i/122 */
+#define SXGBE_CSR_300_350M 0x3 /* MDC = clk_csr_i/142 */
+#define SXGBE_CSR_350_400M 0x4 /* MDC = clk_csr_i/162 */
+#define SXGBE_CSR_400_500M 0x5 /* MDC = clk_csr_i/202 */
/* Platfrom data for platform device structure's
* platform_data field
--
2.17.1
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