[PATCH 0/4] arm: Privileged no-access for LPAE

[Catalin Marinas]

On Mon, Sep 28, 2020 at 09:09:07PM +0800, Orson Zhai wrote:
> On Fri, Dec 11, 2015 at 05:21:40PM +0000, Catalin Marinas wrote:
> > On Thu, Dec 10, 2015 at 11:40:44AM -0800, Kees Cook wrote:
> > > [thread necromancy]
> > > 
> > > This series looks good to me. I'd love to see it accepted. At the very
> > > least the cleanups look like no-brainers. :)
> > > 
> > > Please consider the series:
> > > 
> > > Reviewed-by: Kees Cook <keescook at chromium.org>
> > > 
> > > Thanks for working on it!
> > 
> > Thanks for the review. After some more (internal) discussions around
> > these patches, I need to get clarification on the architecture whether
> > changing the TTBCR.A1 bit is enough to guarantee an ASID change (I do
> 
> Did you check it after then? Now I have a real requirement for implementing
> LPAE and PAN at the same time. So I'd like to know if this patch could work.
> I had some talk with Will about it at other place. He thought this patch is
> not in correct state.
> 
> May I have your latest opinions?

It may work on specific 32-bit CPU implementations but it's not
guaranteed since the TTBCR.A1 bit is allowed to be cached in the TLB. If
you have a CPU implementation in mind, you could check with the
microarchitects whether A1 is cached in the TLB. But since that's not
universally applicable, the patchset cannot be merged into mainline.

I haven't touched these patches for the past 5 years, so I can't tell
whether they still apply.

-- 
Catalin