[PATCH 0/4] arm: Privileged no-access for LPAE

[Orson Zhai]

Hi Catalin,

On Fri, Dec 11, 2015 at 05:21:40PM +0000, Catalin Marinas wrote:
> On Thu, Dec 10, 2015 at 11:40:44AM -0800, Kees Cook wrote:
> > [thread necromancy]
> > 
> > This series looks good to me. I'd love to see it accepted. At the very
> > least the cleanups look like no-brainers. :)
> > 
> > Please consider the series:
> > 
> > Reviewed-by: Kees Cook <keescook at chromium.org>
> > 
> > Thanks for working on it!
> 
> Thanks for the review. After some more (internal) discussions around
> these patches, I need to get clarification on the architecture whether
> changing the TTBCR.A1 bit is enough to guarantee an ASID change (I do

Did you check it after then? Now I have a real requirement for implementing
LPAE and PAN at the same time. So I'd like to know if this patch could work.
I had some talk with Will about it at other place. He thought this patch is
not in correct state.

May I have your latest opinions?

Thanks.

-Orson

> this trick to change to the reserved ASID and avoid TLB invalidation as
> normally required by changes to translation control registers). If
> that's not allowed by the architecture, I would have to change the
> patches to switch to a reserved TTBR0 rather than disabling TTBR0 walks
> at the TTBCR level.
> 
> -- 
> Catalin