[PATCHv5 2/2] soc: qcom: llcc: Support chipsets that can write to llcc

Stephen Boyd swboyd at chromium.org
Tue Sep 15 12:11:29 EDT 2020

Quoting Sai Prakash Ranjan (2020-09-14 23:55:26)
> From: "Isaac J. Manjarres" <isaacm at codeaurora.org>
> Older chipsets may not be allowed to configure certain LLCC registers
> as that is handled by the secure side software. However, this is not
> the case for newer chipsets and they must configure these registers
> according to the contents of the SCT table, while keeping in mind that
> older targets may not have these capabilities. So add support to allow
> such configuration of registers to enable capacity based allocation
> and power collapse retention for capable chipsets.
> Reason for choosing capacity based allocation rather than the default
> way based allocation is because capacity based allocation allows more
> finer grain partition and provides more flexibility in configuration.
> As for the retention through power collapse, it has an advantage where
> the cache hits are more when we wake up from power collapse although
> it does burn more power but the exact power numbers are not known at
> the moment.
> Signed-off-by: Isaac J. Manjarres <isaacm at codeaurora.org>
> Reviewed-by: Douglas Anderson <dianders at chromium.org>
> [saiprakash.ranjan at codeaurora.org: use existing config and reword commit msg]
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan at codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd at chromium.org>

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