[PATCH 2/2] arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files

[Florian Fainelli]

On 10/28/2020 3:11 AM, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal at milecki.pl>
> 
> They don't descibe hardware fully yet but it's enough to boot a system.
> 
> Some missing blocks:
> 1. PMC (Power Management Controller?)
> 2. Crypto
> 3. Thermal
> 
> Asus misses defining full NAND partitions layout and buttons.
> 
> Further changes will fill those gaps as soon as required bindings will
> be found / tested / added.
> 
> Signed-off-by: Rafał Miłecki <rafal at milecki.pl>
> ---

[snip]

> +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/dts-v1/;
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		bootargs = "earlycon=bcm63xx_uart,0xff800640";

These bootargs should be dropped from the

> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";

Please drop "arm,cortex-a53"

> +			reg = <0x0>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu1: cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
> +			reg = <0x1>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0xfff8>;
> +			next-level-cache = <&l2>;

The device that you have access to did not even ship with a version of PSCI?

> +		};
> +
> +		cpu2: cpu at 2 {
> +			device_type = "cpu";
> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
> +			reg = <0x2>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0xfff8>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu3: cpu at 3 {
> +			device_type = "cpu";
> +			compatible = "brcm,cortex-b53", "arm,cortex-a53";
> +			reg = <0x3>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0xfff8>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		l2: l2-cache0 {
> +			compatible = "cache";
> +		};
> +	};
> +
> +	gic: interrupt-controller at 81000000 {
> +		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;

You would want to create a node that encapsulates the ARM peripheral
addresses within the SoC's physical address range, see
arch/arm/boot/dts/bcm63138.dtsi for an example with the axi bus node.

[snip]

> +
> +			nandcs: nandcs at 0 {
> +				compatible = "brcm,nandcs";
> +				reg = <0>;
> +				nand-on-flash-bbt;
> +				brcm,nand-has-wp;

Those last two properties should be moved to the board level DTS file.

> +			};
> +		};
> +
> +		reboot {
> +			compatible = "syscon-reboot";
> +			regmap = <&timer>;
> +			offset = <0x34>;
> +			mask = <1>;
> +		};
> +	};
> +};
> 

-- 
Florian