[RFC please help] membarrier: Rewrite sync_core_before_usermode()
luto at kernel.org
Mon Dec 28 13:50:20 EST 2020
On Mon, Dec 28, 2020 at 10:30 AM Jann Horn <jannh at google.com> wrote:
> On Mon, Dec 28, 2020 at 6:14 PM Andy Lutomirski <luto at kernel.org> wrote:
> > On Mon, Dec 28, 2020 at 2:25 AM Russell King - ARM Linux admin
> > <linux at armlinux.org.uk> wrote:
> > >
> > > On Sun, Dec 27, 2020 at 01:36:13PM -0800, Andy Lutomirski wrote:
> > > > On Sun, Dec 27, 2020 at 12:18 PM Mathieu Desnoyers
> > > > <mathieu.desnoyers at efficios.com> wrote:
> > > > >
> > > > > ----- On Dec 27, 2020, at 1:28 PM, Andy Lutomirski luto at kernel.org wrote:
> > > > >
> > > >
> > > > > >
> > > > > > I admit that I'm rather surprised that the code worked at all on arm64,
> > > > > > and I'm suspicious that it has never been very well tested. My apologies
> > > > > > for not reviewing this more carefully in the first place.
> > > > >
> > > > > Please refer to Documentation/features/sched/membarrier-sync-core/arch-support.txt
> > > > >
> > > > > It clearly states that only arm, arm64, powerpc and x86 support the membarrier
> > > > > sync core feature as of now:
> > > >
> > > > Sigh, I missed arm (32). Russell or ARM folks, what's the right
> > > > incantation to make the CPU notice instruction changes initiated by
> > > > other cores on 32-bit ARM?
> > >
> > > You need to call flush_icache_range(), since the changes need to be
> > > flushed from the data cache to the point of unification (of the Harvard
> > > I and D), and the instruction cache needs to be invalidated so it can
> > > then see those updated instructions. This will also take care of the
> > > necessary barriers that the CPU requires for you.
> > With what parameters? From looking at the header, this is for the
> > case in which the kernel writes some memory and then intends to
> > execute it. That's not what membarrier() does at all. membarrier()
> > works like this:
> > User thread 1:
> > write to RWX memory *or* write to an RW alias of an X region.
> > membarrier(...);
> > somehow tell thread 2 that we're ready (with a store release, perhaps,
> > or even just a relaxed store.)
> > User thread 2:
> > wait for the indication from thread 1.
> > barrier();
> > jump to the code.
> > membarrier() is, for better or for worse, not given a range of addresses.
> > On x86, the documentation is a bit weak, but a strict reading
> > indicates that thread 2 must execute a serializing instruction at some
> > point after thread 1 writes the code and before thread 2 runs it.
> > membarrier() does this by sending an IPI and ensuring that a
> > "serializing" instruction (thanks for great terminology, Intel) is
> > executed. Note that flush_icache_range() is a no-op on x86, and I've
> > asked Intel's architects to please clarify their precise rules. No
> > response yet.
> > On arm64, flush_icache_range() seems to send an IPI, and that's not
> > what I want. membarrier() already does an IPI.
> After chatting with rmk about this (but without claiming that any of
> this is his opinion), based on the manpage, I think membarrier()
> currently doesn't really claim to be synchronizing caches? It just
> serializes cores. So arguably if userspace wants to use membarrier()
> to synchronize code changes, userspace should first do the code
> change, then flush icache as appropriate for the architecture, and
> then do the membarrier() to ensure that the old code is unused?
I haven't the faintest clue what "serializes cores" means. It seems
to be a bit of a mishmash of x86 SDM terminology and Linux x86
"sync_core" terminology. The latter means very little to me, even as
an x86 person.
I'm moderately confident that the *intent* is that a multithreaded
program can write some JIT code to memory, do this membarrier()
operation, and then execute the code, and it will work. Maybe it's
even intended to work cross-architecture without any additional help
from the program. But maybe the existing API is simply incorrect for
> For 32-bit arm, rmk pointed out that that would be the cacheflush()
> syscall. That might cause you to end up with two IPIs instead of one
> in total, but we probably don't care _that_ much about extra IPIs on
> 32-bit arm?
> For arm64, I believe userspace can flush icache across the entire
> system with some instructions from userspace - "DC CVAU" followed by
> "DSB ISH", or something like that, I think? (See e.g.
> compat_arm_syscall(), the arm64 compat code that implements the 32-bit
> arm cacheflush() syscall.)
I have no idea what DC anything does. Based on my very cursory
reading of the manual, ISB is the right approach, but I don't pretend
I understand all the details.
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