[PATCH v6 0/4] mmc: sdhci-of-arasan: Enable UHS-1 support for Keem Bay SOC
andriy.shevchenko at intel.com
Wed Dec 2 07:25:20 EST 2020
On Wed, Dec 02, 2020 at 11:53:42AM +0100, Ulf Hansson wrote:
> On Wed, 2 Dec 2020 at 08:02, <muhammad.husaini.zulkifli at intel.com> wrote:
> > Kindly help to review this patch set.
> This version looks a lot better to me, but I am still requesting you
> to model the pinctrl correctly. I don't see a reason not to, but I may
> have overlooked some things.
I'm wondering why we need to mock up a pin control from something which has no
pin control interface. It's rather communication with firmware that does pin
control under the hood, but it also may be different hardware in the other /
future generations. Would you accept mocking up the same calls over the kernel
as pin control, as something else?
> Would you mind to re-submit to include the gpio/pinctlr list and the
> maintainers, to get their opinion.
And I will send immediately the same comment which I believe Linus W. supports.
But who knows...
Cc'ed to Linus as I mentioned him.
With Best Regards,
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