[EXT] [PATCH 1/2] arm64: dts: marvell: fix interrupt-map property for Armada CP110 master PCIe controller

[Yehuda Yitschak]

Yes...but 

That zero you removed is the "parent unit address" according to the "interrupt-map" documentation 

	parent unit address  - The unit address in the domain of the interrupt parent. The number of 32-bit
			            cells required to specify this address is described by the #address-cells property of the node
			           pointed to by the interrupt-parent field.

Now,  the gic has #address-cells =  <0x1>
And the icu has  #address-cells = <0x0>

So when switching to ICU, the parent unit address was no longer needed and should have been removed 

Best Regards

Yehuda


> -----Original Message-----
> From: Thomas Petazzoni [mailto:thomas.petazzoni at free-electrons.com]
> Sent: Thursday, September 28, 2017 15:57
> To: Yehuda Yitschak
> Cc: Jason Cooper; Andrew Lunn; Sebastian Hesselbarth; Gregory Clement;
> Nadav Haklai; Hanna Hawa; Antoine Tenart; Miquèl Raynal; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [EXT] [PATCH 1/2] arm64: dts: marvell: fix interrupt-map
> property for Armada CP110 master PCIe controller
> 
> Hello,
> 
> On Thu, 28 Sep 2017 12:52:07 +0000, Yehuda Yitschak wrote:
> 
> > The initial version referenced the GIC interrupt controller.
> > Maybe this issue was introduced during the switch to the ICU  ?
> 
> No, it was not introduced by the switch to the ICU. The switch to the ICU
> looked like this:
> 
> -                       interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34
> IRQ_TYPE_LEVEL_HIGH>;
> -                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24
> IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupts = <ICU_GRP_NSR 24
> + IRQ_TYPE_LEVEL_HIGH>;
> 
> As you can see there was already a bogus "0" after &gic.
> 
> Best regards,
> 
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com