Supporting "software interrupts" in an irqchip driver
Mason
slash.tmp at free.fr
Thu May 11 09:04:38 PDT 2017
Hello Thomas, Marc, Mark, (and the funky bunch)
The interrupt controller on my SoC supports so-called "software"
interrupts, meaning that the HW exposes a 32-bit register in which
SW can write some value.
If the value written is non-zero, then interrupt 0 is raised.
How is such a contraption defined in a device tree?
Are there good drivers to read as examples?
drivers/irqchip/irq-mips-cpu.c mentions "software interrupts"
in the context of "which we don't really use or support."
Regards.
More information about the linux-arm-kernel
mailing list