[PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask

[Linus Walleij]

On Fri, Jun 23, 2017 at 2:29 PM, Gregory CLEMENT
<gregory.clement at free-electrons.com> wrote:

> From: Ken Ma <make at marvell.com>
>
> If north bridge selection register bit1 is clear, pins [10:8] are for
> SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
> GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
> and CTSn, so bit1 should be added to uart2 group and it must be set
> for both "gpio" and "uart" functions of uart2 group.
>
> Signed-off-by: Ken Ma <make at marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>

Patch applied.

Yours,
Linus Walleij