[PATCH v2 1/2] arm64: dts: mediatek: Factor out mt817x family device tree
Daniel Kurtz
djkurtz at chromium.org
Tue Feb 14 18:13:56 PST 2017
The MT8173 is one of the mt817x family of related parts that share a
common configuration, but a differing number of cores.
Like what arm/juno and marvell/armada-ap806 did, this patch splits
mt8173.dtsi into mt817x.dtsi and mt8173.dtsi. mt817x.dtsi defines the
common blocks for the family and mt8173.dtsi only describes the mt8173
specific cpu map and cooling contributions.
Also rename mt817x-pinfunc.h, since it applies to the whole family.
Signed-off-by: Yidi Lin <yidi.lin at mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz at chromium.org>
---
Changes in v2:
- Add mt8176 in its own patch.
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 1304 +-------------------
.../{mt8173-pinfunc.h => mt817x-pinfunc.h} | 0
arch/arm64/boot/dts/mediatek/mt817x.dtsi | 1226 ++++++++++++++++++
3 files changed, 1276 insertions(+), 1254 deletions(-)
rename arch/arm64/boot/dts/mediatek/{mt8173-pinfunc.h => mt817x-pinfunc.h} (100%)
create mode 100644 arch/arm64/boot/dts/mediatek/mt817x.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d80ddb4a4a05..03dc3c1da4b2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -11,1281 +11,77 @@
* GNU General Public License for more details.
*/
-#include <dt-bindings/clock/mt8173-clk.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/memory/mt8173-larb-port.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/power/mt8173-power.h>
-#include <dt-bindings/reset/mt8173-resets.h>
-#include "mt8173-pinfunc.h"
+#include "mt817x.dtsi"
/ {
compatible = "mediatek,mt8173";
- interrupt-parent = <&sysirq>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- ovl0 = &ovl0;
- ovl1 = &ovl1;
- rdma0 = &rdma0;
- rdma1 = &rdma1;
- rdma2 = &rdma2;
- wdma0 = &wdma0;
- wdma1 = &wdma1;
- color0 = &color0;
- color1 = &color1;
- split0 = &split0;
- split1 = &split1;
- dpi0 = &dpi0;
- dsi0 = &dsi0;
- dsi1 = &dsi1;
- mdp_rdma0 = &mdp_rdma0;
- mdp_rdma1 = &mdp_rdma1;
- mdp_rsz0 = &mdp_rsz0;
- mdp_rsz1 = &mdp_rsz1;
- mdp_rsz2 = &mdp_rsz2;
- mdp_wdma0 = &mdp_wdma0;
- mdp_wrot0 = &mdp_wrot0;
- mdp_wrot1 = &mdp_wrot1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+};
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
+&cpus {
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
};
-
- cluster1 {
- core0 {
- cpu = <&cpu2>;
- };
- core1 {
- cpu = <&cpu3>;
- };
+ core1 {
+ cpu = <&cpu1>;
};
};
- cpu0: cpu at 0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x000>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- };
-
- cpu1: cpu at 1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x001>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- };
-
- cpu2: cpu at 100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x100>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- };
-
- cpu3: cpu at 101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x101>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- local-timer-stop;
- entry-latency-us = <639>;
- exit-latency-us = <680>;
- min-residency-us = <1088>;
- arm,psci-suspend-param = <0x0010000>;
+ cluster1 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ core1 {
+ cpu = <&cpu3>;
};
};
};
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
- method = "smc";
- cpu_suspend = <0x84000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0x84000003>;
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- clk26m: oscillator at 0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <26000000>;
- clock-output-names = "clk26m";
- };
-
- clk32k: oscillator at 1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32000>;
- clock-output-names = "clk32k";
- };
-
- cpum_ck: oscillator at 2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "cpum_ck";
- };
-
- thermal-zones {
- cpu_thermal: cpu_thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
-
- thermal-sensors = <&thermal>;
- sustainable-power = <1500>; /* milliwatts */
-
- trips {
- threshold: trip-point at 0 {
- temperature = <68000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- target: trip-point at 1 {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu_crit at 0 {
- temperature = <115000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map at 0 {
- trip = <&target>;
- cooling-device = <&cpu0 0 0>;
- contribution = <3072>;
- };
- map at 1 {
- trip = <&target>;
- cooling-device = <&cpu2 0 0>;
- contribution = <1024>;
- };
- };
- };
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- vpu_dma_reserved: vpu_dma_mem_region {
- compatible = "shared-dma-pool";
- reg = <0 0xb7000000 0 0x500000>;
- alignment = <0x1000>;
- no-map;
- };
+ cpu2: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ cpu3: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
+};
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- ranges;
-
- topckgen: clock-controller at 10000000 {
- compatible = "mediatek,mt8173-topckgen";
- reg = <0 0x10000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- infracfg: power-controller at 10001000 {
- compatible = "mediatek,mt8173-infracfg", "syscon";
- reg = <0 0x10001000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- pericfg: power-controller at 10003000 {
- compatible = "mediatek,mt8173-pericfg", "syscon";
- reg = <0 0x10003000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- syscfg_pctl_a: syscfg_pctl_a at 10005000 {
- compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
- reg = <0 0x10005000 0 0x1000>;
- };
-
- pio: pinctrl at 0x10005000 {
- compatible = "mediatek,mt8173-pinctrl";
- reg = <0 0x1000b000 0 0x1000>;
- mediatek,pctl-regmap = <&syscfg_pctl_a>;
- pins-are-numbered;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-
- hdmi_pin: xxx {
-
- /*hdmi htplg pin*/
- pins1 {
- pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
- input-enable;
- bias-pull-down;
- };
- };
-
- i2c0_pins_a: i2c0 {
- pins1 {
- pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
- <MT8173_PIN_46_SCL0__FUNC_SCL0>;
- bias-disable;
- };
- };
-
- i2c1_pins_a: i2c1 {
- pins1 {
- pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
- <MT8173_PIN_126_SCL1__FUNC_SCL1>;
- bias-disable;
- };
- };
-
- i2c2_pins_a: i2c2 {
- pins1 {
- pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
- <MT8173_PIN_44_SCL2__FUNC_SCL2>;
- bias-disable;
- };
- };
-
- i2c3_pins_a: i2c3 {
- pins1 {
- pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
- <MT8173_PIN_107_SCL3__FUNC_SCL3>;
- bias-disable;
- };
- };
-
- i2c4_pins_a: i2c4 {
- pins1 {
- pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
- <MT8173_PIN_134_SCL4__FUNC_SCL4>;
- bias-disable;
- };
- };
-
- i2c6_pins_a: i2c6 {
- pins1 {
- pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
- <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
- bias-disable;
- };
- };
- };
-
- scpsys: scpsys at 10006000 {
- compatible = "mediatek,mt8173-scpsys";
- #power-domain-cells = <1>;
- reg = <0 0x10006000 0 0x1000>;
- clocks = <&clk26m>,
- <&topckgen CLK_TOP_MM_SEL>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "mfg", "mm", "venc", "venc_lt";
- infracfg = <&infracfg>;
- };
-
- watchdog: watchdog at 10007000 {
- compatible = "mediatek,mt8173-wdt",
- "mediatek,mt6589-wdt";
- reg = <0 0x10007000 0 0x100>;
- };
-
- timer: timer at 10008000 {
- compatible = "mediatek,mt8173-timer",
- "mediatek,mt6577-timer";
- reg = <0 0x10008000 0 0x1000>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_CLK_13M>,
- <&topckgen CLK_TOP_RTC_SEL>;
- };
-
- pwrap: pwrap at 1000d000 {
- compatible = "mediatek,mt8173-pwrap";
- reg = <0 0x1000d000 0 0x1000>;
- reg-names = "pwrap";
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
- reset-names = "pwrap";
- clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
- clock-names = "spi", "wrap";
- };
-
- cec: cec at 10013000 {
- compatible = "mediatek,mt8173-cec";
- reg = <0 0x10013000 0 0xbc>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_CEC>;
- status = "disabled";
- };
-
- vpu: vpu at 10020000 {
- compatible = "mediatek,mt8173-vpu";
- reg = <0 0x10020000 0 0x30000>,
- <0 0x10050000 0 0x100>;
- reg-names = "tcm", "cfg_reg";
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_SCP_SEL>;
- clock-names = "main";
- memory-region = <&vpu_dma_reserved>;
- };
-
- sysirq: intpol-controller at 10200620 {
- compatible = "mediatek,mt8173-sysirq",
- "mediatek,mt6577-sysirq";
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- reg = <0 0x10200620 0 0x20>;
- };
-
- iommu: iommu at 10205000 {
- compatible = "mediatek,mt8173-m4u";
- reg = <0 0x10205000 0 0x1000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_M4U>;
- clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2
- &larb3 &larb4 &larb5>;
- #iommu-cells = <1>;
- };
-
- efuse: efuse at 10206000 {
- compatible = "mediatek,mt8173-efuse";
- reg = <0 0x10206000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- thermal_calibration: calib at 528 {
- reg = <0x528 0xc>;
- };
- };
-
- apmixedsys: clock-controller at 10209000 {
- compatible = "mediatek,mt8173-apmixedsys";
- reg = <0 0x10209000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- hdmi_phy: hdmi-phy at 10209100 {
- compatible = "mediatek,mt8173-hdmi-phy";
- reg = <0 0x10209100 0 0x24>;
- clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
- clock-names = "pll_ref";
- clock-output-names = "hdmitx_dig_cts";
- mediatek,ibias = <0xa>;
- mediatek,ibias_up = <0x1c>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- mipi_tx0: mipi-dphy at 10215000 {
- compatible = "mediatek,mt8173-mipi-tx";
- reg = <0 0x10215000 0 0x1000>;
- clocks = <&clk26m>;
- clock-output-names = "mipi_tx0_pll";
- #clock-cells = <0>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- mipi_tx1: mipi-dphy at 10216000 {
- compatible = "mediatek,mt8173-mipi-tx";
- reg = <0 0x10216000 0 0x1000>;
- clocks = <&clk26m>;
- clock-output-names = "mipi_tx1_pll";
- #clock-cells = <0>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller at 10220000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- interrupt-controller;
- reg = <0 0x10221000 0 0x1000>,
- <0 0x10222000 0 0x2000>,
- <0 0x10224000 0 0x2000>,
- <0 0x10226000 0 0x2000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- auxadc: auxadc at 11001000 {
- compatible = "mediatek,mt8173-auxadc";
- reg = <0 0x11001000 0 0x1000>;
- clocks = <&pericfg CLK_PERI_AUXADC>;
- clock-names = "main";
- #io-channel-cells = <1>;
- };
-
- uart0: serial at 11002000 {
- compatible = "mediatek,mt8173-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11002000 0 0x400>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- uart1: serial at 11003000 {
- compatible = "mediatek,mt8173-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11003000 0 0x400>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- uart2: serial at 11004000 {
- compatible = "mediatek,mt8173-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11004000 0 0x400>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- uart3: serial at 11005000 {
- compatible = "mediatek,mt8173-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11005000 0 0x400>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- i2c0: i2c at 11007000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11007000 0 0x70>,
- <0 0x11000100 0 0x80>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C0>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c at 11008000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11008000 0 0x70>,
- <0 0x11000180 0 0x80>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C1>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c at 11009000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11009000 0 0x70>,
- <0 0x11000200 0 0x80>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C2>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi: spi at 1100a000 {
- compatible = "mediatek,mt8173-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0 0x1100a000 0 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&pericfg CLK_PERI_SPI0>;
- clock-names = "parent-clk", "sel-clk", "spi-clk";
- status = "disabled";
- };
-
- thermal: thermal at 1100b000 {
- #thermal-sensor-cells = <0>;
- compatible = "mediatek,mt8173-thermal";
- reg = <0 0x1100b000 0 0x1000>;
- interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
- clock-names = "therm", "auxadc";
- resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
- mediatek,auxadc = <&auxadc>;
- mediatek,apmixedsys = <&apmixedsys>;
- nvmem-cells = <&thermal_calibration>;
- nvmem-cell-names = "calibration-data";
- };
-
- nor_flash: spi at 1100d000 {
- compatible = "mediatek,mt8173-nor";
- reg = <0 0x1100d000 0 0xe0>;
- clocks = <&pericfg CLK_PERI_SPI>,
- <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
- clock-names = "spi", "sf";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c at 11010000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11010000 0 0x70>,
- <0 0x11000280 0 0x80>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C3>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c at 11011000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11011000 0 0x70>,
- <0 0x11000300 0 0x80>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C4>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- hdmiddc0: i2c at 11012000 {
- compatible = "mediatek,mt8173-hdmi-ddc";
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
- reg = <0 0x11012000 0 0x1C>;
- clocks = <&pericfg CLK_PERI_I2C5>;
- clock-names = "ddc-i2c";
- };
-
- i2c6: i2c at 11013000 {
- compatible = "mediatek,mt8173-i2c";
- reg = <0 0x11013000 0 0x70>,
- <0 0x11000080 0 0x80>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C6>,
- <&pericfg CLK_PERI_AP_DMA>;
- clock-names = "main", "dma";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_pins_a>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- afe: audio-controller at 11220000 {
- compatible = "mediatek,mt8173-afe-pcm";
- reg = <0 0x11220000 0 0x1000>;
- interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
- clocks = <&infracfg CLK_INFRA_AUDIO>,
- <&topckgen CLK_TOP_AUDIO_SEL>,
- <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
- <&topckgen CLK_TOP_APLL1_DIV0>,
- <&topckgen CLK_TOP_APLL2_DIV0>,
- <&topckgen CLK_TOP_I2S0_M_SEL>,
- <&topckgen CLK_TOP_I2S1_M_SEL>,
- <&topckgen CLK_TOP_I2S2_M_SEL>,
- <&topckgen CLK_TOP_I2S3_M_SEL>,
- <&topckgen CLK_TOP_I2S3_B_SEL>;
- clock-names = "infra_sys_audio_clk",
- "top_pdn_audio",
- "top_pdn_aud_intbus",
- "bck0",
- "bck1",
- "i2s0_m",
- "i2s1_m",
- "i2s2_m",
- "i2s3_m",
- "i2s3_b";
- assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
- <&topckgen CLK_TOP_AUD_2_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
- <&topckgen CLK_TOP_APLL2>;
- };
-
- mmc0: mmc at 11230000 {
- compatible = "mediatek,mt8173-mmc",
- "mediatek,mt8135-mmc";
- reg = <0 0x11230000 0 0x1000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_0>,
- <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- mmc1: mmc at 11240000 {
- compatible = "mediatek,mt8173-mmc",
- "mediatek,mt8135-mmc";
- reg = <0 0x11240000 0 0x1000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_1>,
- <&topckgen CLK_TOP_AXI_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- mmc2: mmc at 11250000 {
- compatible = "mediatek,mt8173-mmc",
- "mediatek,mt8135-mmc";
- reg = <0 0x11250000 0 0x1000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_2>,
- <&topckgen CLK_TOP_AXI_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- mmc3: mmc at 11260000 {
- compatible = "mediatek,mt8173-mmc",
- "mediatek,mt8135-mmc";
- reg = <0 0x11260000 0 0x1000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_3>,
- <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- ssusb: usb at 11271000 {
- compatible = "mediatek,mt8173-mtu3";
- reg = <0 0x11271000 0 0x3000>,
- <0 0x11280700 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
- phys = <&phy_port0 PHY_TYPE_USB3>,
- <&phy_port1 PHY_TYPE_USB2>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>,
- <&pericfg CLK_PERI_USB0>,
- <&pericfg CLK_PERI_USB1>;
- clock-names = "sys_ck",
- "wakeup_deb_p0",
- "wakeup_deb_p1";
- mediatek,syscon-wakeup = <&pericfg>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- usb_host: xhci at 11270000 {
- compatible = "mediatek,mt8173-xhci";
- reg = <0 0x11270000 0 0x1000>;
- reg-names = "mac";
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>;
- clock-names = "sys_ck";
- status = "disabled";
- };
- };
-
- u3phy: usb-phy at 11290000 {
- compatible = "mediatek,mt8173-u3phy";
- reg = <0 0x11290000 0 0x800>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "u3phya_ref";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "okay";
-
- phy_port0: port at 11290800 {
- reg = <0 0x11290800 0 0x800>;
- #phy-cells = <1>;
- status = "okay";
- };
-
- phy_port1: port at 11291000 {
- reg = <0 0x11291000 0 0x800>;
- #phy-cells = <1>;
- status = "okay";
- };
- };
-
- mmsys: clock-controller at 14000000 {
- compatible = "mediatek,mt8173-mmsys", "syscon";
- reg = <0 0x14000000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
- assigned-clock-rates = <400000000>;
- #clock-cells = <1>;
- };
-
- mdp {
- compatible = "mediatek,mt8173-mdp";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- mediatek,vpu = <&vpu>;
-
- mdp_rdma0: rdma at 14001000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- reg = <0 0x14001000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA0>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,larb = <&larb0>;
- };
-
- mdp_rdma1: rdma at 14002000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- reg = <0 0x14002000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA1>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- mediatek,larb = <&larb4>;
- };
-
- mdp_rsz0: rsz at 14003000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14003000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_rsz1: rsz at 14004000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14004000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_rsz2: rsz at 14005000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14005000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ2>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_wdma0: wdma at 14006000 {
- compatible = "mediatek,mt8173-mdp-wdma";
- reg = <0 0x14006000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WDMA>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WDMA>;
- mediatek,larb = <&larb0>;
- };
-
- mdp_wrot0: wrot at 14007000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14007000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT0>;
- mediatek,larb = <&larb0>;
- };
-
- mdp_wrot1: wrot at 14008000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14008000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT1>;
- mediatek,larb = <&larb4>;
- };
- };
-
- ovl0: ovl at 1400c000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400c000 0 0x1000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL0>;
- iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
- };
-
- ovl1: ovl at 1400d000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400d000 0 0x1000>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL1>;
- iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
- };
-
- rdma0: rdma at 1400e000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400e000 0 0x1000>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA0>;
- iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
- };
-
- rdma1: rdma at 1400f000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400f000 0 0x1000>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA1>;
- iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
- };
-
- rdma2: rdma at 14010000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x14010000 0 0x1000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA2>;
- iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
- };
-
- wdma0: wdma at 14011000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14011000 0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA0>;
- iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
- };
-
- wdma1: wdma at 14012000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14012000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA1>;
- iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
- };
-
- color0: color at 14013000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14013000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR0>;
- };
-
- color1: color at 14014000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14014000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR1>;
- };
-
- aal at 14015000 {
- compatible = "mediatek,mt8173-disp-aal";
- reg = <0 0x14015000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_AAL>;
- };
-
- gamma at 14016000 {
- compatible = "mediatek,mt8173-disp-gamma";
- reg = <0 0x14016000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_GAMMA>;
- };
-
- merge at 14017000 {
- compatible = "mediatek,mt8173-disp-merge";
- reg = <0 0x14017000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_MERGE>;
- };
-
- split0: split at 14018000 {
- compatible = "mediatek,mt8173-disp-split";
- reg = <0 0x14018000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
- };
-
- split1: split at 14019000 {
- compatible = "mediatek,mt8173-disp-split";
- reg = <0 0x14019000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
- };
-
- ufoe at 1401a000 {
- compatible = "mediatek,mt8173-disp-ufoe";
- reg = <0 0x1401a000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_UFOE>;
- };
-
- dsi0: dsi at 1401b000 {
- compatible = "mediatek,mt8173-dsi";
- reg = <0 0x1401b000 0 0x1000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
- <&mmsys CLK_MM_DSI0_DIGITAL>,
- <&mipi_tx0>;
- clock-names = "engine", "digital", "hs";
- phys = <&mipi_tx0>;
- phy-names = "dphy";
- status = "disabled";
- };
-
- dsi1: dsi at 1401c000 {
- compatible = "mediatek,mt8173-dsi";
- reg = <0 0x1401c000 0 0x1000>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
- <&mmsys CLK_MM_DSI1_DIGITAL>,
- <&mipi_tx1>;
- clock-names = "engine", "digital", "hs";
- phy = <&mipi_tx1>;
- phy-names = "dphy";
- status = "disabled";
- };
-
- dpi0: dpi at 1401d000 {
- compatible = "mediatek,mt8173-dpi";
- reg = <0 0x1401d000 0 0x1000>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DPI_PIXEL>,
- <&mmsys CLK_MM_DPI_ENGINE>,
- <&apmixedsys CLK_APMIXED_TVDPLL>;
- clock-names = "pixel", "engine", "pll";
- status = "disabled";
-
- port {
- dpi0_out: endpoint {
- remote-endpoint = <&hdmi0_in>;
- };
- };
- };
-
- pwm0: pwm at 1401e000 {
- compatible = "mediatek,mt8173-disp-pwm",
- "mediatek,mt6595-disp-pwm";
- reg = <0 0x1401e000 0 0x1000>;
- #pwm-cells = <2>;
- clocks = <&mmsys CLK_MM_DISP_PWM026M>,
- <&mmsys CLK_MM_DISP_PWM0MM>;
- clock-names = "main", "mm";
- status = "disabled";
- };
-
- pwm1: pwm at 1401f000 {
- compatible = "mediatek,mt8173-disp-pwm",
- "mediatek,mt6595-disp-pwm";
- reg = <0 0x1401f000 0 0x1000>;
- #pwm-cells = <2>;
- clocks = <&mmsys CLK_MM_DISP_PWM126M>,
- <&mmsys CLK_MM_DISP_PWM1MM>;
- clock-names = "main", "mm";
- status = "disabled";
- };
-
- mutex: mutex at 14020000 {
- compatible = "mediatek,mt8173-disp-mutex";
- reg = <0 0x14020000 0 0x1000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_MUTEX_32K>;
- };
-
- larb0: larb at 14021000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x14021000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_SMI_LARB0>,
- <&mmsys CLK_MM_SMI_LARB0>;
- clock-names = "apb", "smi";
- };
-
- smi_common: smi at 14022000 {
- compatible = "mediatek,mt8173-smi-common";
- reg = <0 0x14022000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_SMI_COMMON>,
- <&mmsys CLK_MM_SMI_COMMON>;
- clock-names = "apb", "smi";
- };
-
- od at 14023000 {
- compatible = "mediatek,mt8173-disp-od";
- reg = <0 0x14023000 0 0x1000>;
- clocks = <&mmsys CLK_MM_DISP_OD>;
- };
-
- hdmi0: hdmi at 14025000 {
- compatible = "mediatek,mt8173-hdmi";
- reg = <0 0x14025000 0 0x400>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
- <&mmsys CLK_MM_HDMI_PLLCK>,
- <&mmsys CLK_MM_HDMI_AUDIO>,
- <&mmsys CLK_MM_HDMI_SPDIF>;
- clock-names = "pixel", "pll", "bclk", "spdif";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pin>;
- phys = <&hdmi_phy>;
- phy-names = "hdmi";
- mediatek,syscon-hdmi = <&mmsys 0x900>;
- assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
- assigned-clock-parents = <&hdmi_phy>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port at 0 {
- reg = <0>;
-
- hdmi0_in: endpoint {
- remote-endpoint = <&dpi0_out>;
- };
- };
- };
- };
-
- larb4: larb at 14027000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x14027000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_SMI_LARB4>,
- <&mmsys CLK_MM_SMI_LARB4>;
- clock-names = "apb", "smi";
- };
-
- imgsys: clock-controller at 15000000 {
- compatible = "mediatek,mt8173-imgsys", "syscon";
- reg = <0 0x15000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- larb2: larb at 15001000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x15001000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
- clocks = <&imgsys CLK_IMG_LARB2_SMI>,
- <&imgsys CLK_IMG_LARB2_SMI>;
- clock-names = "apb", "smi";
- };
-
- vdecsys: clock-controller at 16000000 {
- compatible = "mediatek,mt8173-vdecsys", "syscon";
- reg = <0 0x16000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- vcodec_dec: vcodec at 16000000 {
- compatible = "mediatek,mt8173-vcodec-dec";
- reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
- <0 0x16020000 0 0x1000>, /* VDEC_MISC */
- <0 0x16021000 0 0x800>, /* VDEC_LD */
- <0 0x16021800 0 0x800>, /* VDEC_TOP */
- <0 0x16022000 0 0x1000>, /* VDEC_CM */
- <0 0x16023000 0 0x1000>, /* VDEC_AD */
- <0 0x16024000 0 0x1000>, /* VDEC_AV */
- <0 0x16025000 0 0x1000>, /* VDEC_PP */
- <0 0x16026800 0 0x800>, /* VDEC_HWD */
- <0 0x16027000 0 0x800>, /* VDEC_HWQ */
- <0 0x16027800 0 0x800>, /* VDEC_HWB */
- <0 0x16028400 0 0x400>; /* VDEC_HWG */
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb1>;
- iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
- <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
- <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
- <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
- <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
- <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
- <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
- <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
- mediatek,vpu = <&vpu>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
- clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
- <&topckgen CLK_TOP_UNIVPLL_D2>,
- <&topckgen CLK_TOP_CCI400_SEL>,
- <&topckgen CLK_TOP_VDEC_SEL>,
- <&topckgen CLK_TOP_VCODECPLL>,
- <&apmixedsys CLK_APMIXED_VENCPLL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>,
- <&topckgen CLK_TOP_VCODECPLL_370P5>;
- clock-names = "vcodecpll",
- "univpll_d2",
- "clk_cci400_sel",
- "vdec_sel",
- "vdecpll",
- "vencpll",
- "venc_lt_sel",
- "vdec_bus_clk_src";
- };
-
- larb1: larb at 16010000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x16010000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
- clocks = <&vdecsys CLK_VDEC_CKEN>,
- <&vdecsys CLK_VDEC_LARB_CKEN>;
- clock-names = "apb", "smi";
- };
-
- vencsys: clock-controller at 18000000 {
- compatible = "mediatek,mt8173-vencsys", "syscon";
- reg = <0 0x18000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- larb3: larb at 18001000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x18001000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
- clocks = <&vencsys CLK_VENC_CKE1>,
- <&vencsys CLK_VENC_CKE0>;
- clock-names = "apb", "smi";
- };
-
- vcodec_enc: vcodec at 18002000 {
- compatible = "mediatek,mt8173-vcodec-enc";
- reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
- <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>,
- <&larb5>;
- iommus = <&iommu M4U_PORT_VENC_RCPU>,
- <&iommu M4U_PORT_VENC_REC>,
- <&iommu M4U_PORT_VENC_BSDMA>,
- <&iommu M4U_PORT_VENC_SV_COMV>,
- <&iommu M4U_PORT_VENC_RD_COMV>,
- <&iommu M4U_PORT_VENC_CUR_LUMA>,
- <&iommu M4U_PORT_VENC_CUR_CHROMA>,
- <&iommu M4U_PORT_VENC_REF_LUMA>,
- <&iommu M4U_PORT_VENC_REF_CHROMA>,
- <&iommu M4U_PORT_VENC_NBM_RDMA>,
- <&iommu M4U_PORT_VENC_NBM_WDMA>,
- <&iommu M4U_PORT_VENC_RCPU_SET2>,
- <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
- <&iommu M4U_PORT_VENC_BSDMA_SET2>,
- <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
- <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
- <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
- mediatek,vpu = <&vpu>;
- clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "venc_sel_src",
- "venc_sel",
- "venc_lt_sel_src",
- "venc_lt_sel";
- };
-
- vencltsys: clock-controller at 19000000 {
- compatible = "mediatek,mt8173-vencltsys", "syscon";
- reg = <0 0x19000000 0 0x1000>;
- #clock-cells = <1>;
+&cpu_thermal {
+ cooling-maps {
+ map at 0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 0 0>;
+ contribution = <3072>;
};
-
- larb5: larb at 19001000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x19001000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
- clocks = <&vencltsys CLK_VENCLT_CKE1>,
- <&vencltsys CLK_VENCLT_CKE0>;
- clock-names = "apb", "smi";
+ map at 1 {
+ trip = <&target>;
+ cooling-device = <&cpu2 0 0>;
+ contribution = <1024>;
};
};
};
-
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt817x-pinfunc.h
similarity index 100%
rename from arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h
rename to arch/arm64/boot/dts/mediatek/mt817x-pinfunc.h
diff --git a/arch/arm64/boot/dts/mediatek/mt817x.dtsi b/arch/arm64/boot/dts/mediatek/mt817x.dtsi
new file mode 100644
index 000000000000..1bfe1edf9964
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt817x.dtsi
@@ -0,0 +1,1226 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Eddie Huang <eddie.huang at mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/mt8173-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/memory/mt8173-larb-port.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/mt8173-power.h>
+#include <dt-bindings/reset/mt8173-resets.h>
+#include "mt817x-pinfunc.h"
+
+/ {
+ compatible = "mediatek,mt817x";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ovl0 = &ovl0;
+ ovl1 = &ovl1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ rdma2 = &rdma2;
+ wdma0 = &wdma0;
+ wdma1 = &wdma1;
+ color0 = &color0;
+ color1 = &color1;
+ split0 = &split0;
+ split1 = &split1;
+ dpi0 = &dpi0;
+ dsi0 = &dsi0;
+ dsi1 = &dsi1;
+ mdp_rdma0 = &mdp_rdma0;
+ mdp_rdma1 = &mdp_rdma1;
+ mdp_rsz0 = &mdp_rsz0;
+ mdp_rsz1 = &mdp_rsz1;
+ mdp_rsz2 = &mdp_rsz2;
+ mdp_wdma0 = &mdp_wdma0;
+ mdp_wrot0 = &mdp_wrot0;
+ mdp_wrot1 = &mdp_wrot1;
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <639>;
+ exit-latency-us = <680>;
+ min-residency-us = <1088>;
+ arm,psci-suspend-param = <0x0010000>;
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ cpu_suspend = <0x84000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ };
+
+ clk26m: oscillator at 0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator at 1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "clk32k";
+ };
+
+ cpum_ck: oscillator at 2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "cpum_ck";
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu_thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&thermal>;
+ sustainable-power = <1500>; /* milliwatts */
+
+ trips {
+ threshold: trip-point at 0 {
+ temperature = <68000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point at 1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit at 0 {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ vpu_dma_reserved: vpu_dma_mem_region {
+ compatible = "shared-dma-pool";
+ reg = <0 0xb7000000 0 0x500000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ topckgen: clock-controller at 10000000 {
+ compatible = "mediatek,mt8173-topckgen";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: power-controller at 10001000 {
+ compatible = "mediatek,mt8173-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: power-controller at 10003000 {
+ compatible = "mediatek,mt8173-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ syscfg_pctl_a: syscfg_pctl_a at 10005000 {
+ compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ pio: pinctrl at 0x10005000 {
+ compatible = "mediatek,mt8173-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+
+ hdmi_pin: xxx {
+
+ /*hdmi htplg pin*/
+ pins1 {
+ pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ i2c0_pins_a: i2c0 {
+ pins1 {
+ pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
+ <MT8173_PIN_46_SCL0__FUNC_SCL0>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c1 {
+ pins1 {
+ pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
+ <MT8173_PIN_126_SCL1__FUNC_SCL1>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins_a: i2c2 {
+ pins1 {
+ pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
+ <MT8173_PIN_44_SCL2__FUNC_SCL2>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins_a: i2c3 {
+ pins1 {
+ pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
+ <MT8173_PIN_107_SCL3__FUNC_SCL3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins_a: i2c4 {
+ pins1 {
+ pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
+ <MT8173_PIN_134_SCL4__FUNC_SCL4>;
+ bias-disable;
+ };
+ };
+
+ i2c6_pins_a: i2c6 {
+ pins1 {
+ pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
+ <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
+ bias-disable;
+ };
+ };
+ };
+
+ scpsys: scpsys at 10006000 {
+ compatible = "mediatek,mt8173-scpsys";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&clk26m>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "mfg", "mm", "venc", "venc_lt";
+ infracfg = <&infracfg>;
+ };
+
+ watchdog: watchdog at 10007000 {
+ compatible = "mediatek,mt8173-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
+ timer: timer at 10008000 {
+ compatible = "mediatek,mt8173-timer",
+ "mediatek,mt6577-timer";
+ reg = <0 0x10008000 0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CLK_13M>,
+ <&topckgen CLK_TOP_RTC_SEL>;
+ };
+
+ pwrap: pwrap at 1000d000 {
+ compatible = "mediatek,mt8173-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
+ reset-names = "pwrap";
+ clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
+ clock-names = "spi", "wrap";
+ };
+
+ cec: cec at 10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ status = "disabled";
+ };
+
+ vpu: vpu at 10020000 {
+ compatible = "mediatek,mt8173-vpu";
+ reg = <0 0x10020000 0 0x30000>,
+ <0 0x10050000 0 0x100>;
+ reg-names = "tcm", "cfg_reg";
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_SCP_SEL>;
+ clock-names = "main";
+ memory-region = <&vpu_dma_reserved>;
+ };
+
+ sysirq: intpol-controller at 10200620 {
+ compatible = "mediatek,mt8173-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200620 0 0x20>;
+ };
+
+ iommu: iommu at 10205000 {
+ compatible = "mediatek,mt8173-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ mediatek,larbs = <&larb0 &larb1 &larb2
+ &larb3 &larb4 &larb5>;
+ #iommu-cells = <1>;
+ };
+
+ efuse: efuse at 10206000 {
+ compatible = "mediatek,mt8173-efuse";
+ reg = <0 0x10206000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ thermal_calibration: calib at 528 {
+ reg = <0x528 0xc>;
+ };
+ };
+
+ apmixedsys: clock-controller at 10209000 {
+ compatible = "mediatek,mt8173-apmixedsys";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ hdmi_phy: hdmi-phy at 10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ clock-output-names = "hdmitx_dig_cts";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_tx0: mipi-dphy at 10215000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10215000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_tx1: mipi-dphy at 10216000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10216000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx1_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller at 10220000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x10221000 0 0x1000>,
+ <0 0x10222000 0 0x2000>,
+ <0 0x10224000 0 0x2000>,
+ <0 0x10226000 0 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ auxadc: auxadc at 11001000 {
+ compatible = "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+
+ uart0: serial at 11002000 {
+ compatible = "mediatek,mt8173-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial at 11003000 {
+ compatible = "mediatek,mt8173-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial at 11004000 {
+ compatible = "mediatek,mt8173-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial at 11005000 {
+ compatible = "mediatek,mt8173-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ i2c0: i2c at 11007000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11007000 0 0x70>,
+ <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 11008000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11008000 0 0x70>,
+ <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 11009000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11009000 0 0x70>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi: spi at 1100a000 {
+ compatible = "mediatek,mt8173-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&pericfg CLK_PERI_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ thermal: thermal at 1100b000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "mediatek,mt8173-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "therm", "auxadc";
+ resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ };
+
+ nor_flash: spi at 1100d000 {
+ compatible = "mediatek,mt8173-nor";
+ reg = <0 0x1100d000 0 0xe0>;
+ clocks = <&pericfg CLK_PERI_SPI>,
+ <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
+ clock-names = "spi", "sf";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 11010000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11010000 0 0x70>,
+ <0 0x11000280 0 0x80>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C3>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c at 11011000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11011000 0 0x70>,
+ <0 0x11000300 0 0x80>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C4>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ hdmiddc0: i2c at 11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ reg = <0 0x11012000 0 0x1C>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+ };
+
+ i2c6: i2c at 11013000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11013000 0 0x70>,
+ <0 0x11000080 0 0x80>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C6>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ afe: audio-controller at 11220000 {
+ compatible = "mediatek,mt8173-afe-pcm";
+ reg = <0 0x11220000 0 0x1000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_APLL1_DIV0>,
+ <&topckgen CLK_TOP_APLL2_DIV0>,
+ <&topckgen CLK_TOP_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_I2S3_B_SEL>;
+ clock-names = "infra_sys_audio_clk",
+ "top_pdn_audio",
+ "top_pdn_aud_intbus",
+ "bck0",
+ "bck1",
+ "i2s0_m",
+ "i2s1_m",
+ "i2s2_m",
+ "i2s3_m",
+ "i2s3_b";
+ assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_AUD_2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_APLL2>;
+ };
+
+ mmc0: mmc at 11230000 {
+ compatible = "mediatek,mt8173-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11230000 0 0x1000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc1: mmc at 11240000 {
+ compatible = "mediatek,mt8173-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11240000 0 0x1000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc2: mmc at 11250000 {
+ compatible = "mediatek,mt8173-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11250000 0 0x1000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_2>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc3: mmc at 11260000 {
+ compatible = "mediatek,mt8173-mmc",
+ "mediatek,mt8135-mmc";
+ reg = <0 0x11260000 0 0x1000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_3>,
+ <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ ssusb: usb at 11271000 {
+ compatible = "mediatek,mt8173-mtu3";
+ reg = <0 0x11271000 0 0x3000>,
+ <0 0x11280700 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&phy_port0 PHY_TYPE_USB3>,
+ <&phy_port1 PHY_TYPE_USB2>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB1>;
+ clock-names = "sys_ck",
+ "wakeup_deb_p0",
+ "wakeup_deb_p1";
+ mediatek,syscon-wakeup = <&pericfg>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: xhci at 11270000 {
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0 0x11270000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
+ };
+
+ u3phy: usb-phy at 11290000 {
+ compatible = "mediatek,mt8173-u3phy";
+ reg = <0 0x11290000 0 0x800>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "u3phya_ref";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ phy_port0: port at 11290800 {
+ reg = <0 0x11290800 0 0x800>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ phy_port1: port at 11291000 {
+ reg = <0 0x11291000 0 0x800>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ mmsys: clock-controller at 14000000 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
+ assigned-clock-rates = <400000000>;
+ #clock-cells = <1>;
+ };
+
+ mdp {
+ compatible = "mediatek,mt8173-mdp";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ mediatek,vpu = <&vpu>;
+
+ mdp_rdma0: rdma at 14001000 {
+ compatible = "mediatek,mt8173-mdp-rdma";
+ reg = <0 0x14001000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_rdma1: rdma at 14002000 {
+ compatible = "mediatek,mt8173-mdp-rdma";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA1>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ mdp_rsz0: rsz at 14003000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14003000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_rsz1: rsz at 14004000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14004000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_rsz2: rsz at 14005000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14005000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ2>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_wdma0: wdma at 14006000 {
+ compatible = "mediatek,mt8173-mdp-wdma";
+ reg = <0 0x14006000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_wrot0: wrot at 14007000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_wrot1: wrot at 14008000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14008000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT1>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT1>;
+ mediatek,larb = <&larb4>;
+ };
+ };
+
+ ovl0: ovl at 1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ovl1: ovl at 1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ rdma0: rdma at 1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma1: rdma at 1400f000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ rdma2: rdma at 14010000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA2>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA2>;
+ mediatek,larb = <&larb4>;
+ };
+
+ wdma0: wdma at 14011000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ wdma1: wdma at 14012000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA1>;
+ mediatek,larb = <&larb4>;
+ };
+
+ color0: color at 14013000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14013000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ };
+
+ color1: color at 14014000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR1>;
+ };
+
+ aal at 14015000 {
+ compatible = "mediatek,mt8173-disp-aal";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+ };
+
+ gamma at 14016000 {
+ compatible = "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+ };
+
+ merge at 14017000 {
+ compatible = "mediatek,mt8173-disp-merge";
+ reg = <0 0x14017000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_MERGE>;
+ };
+
+ split0: split at 14018000 {
+ compatible = "mediatek,mt8173-disp-split";
+ reg = <0 0x14018000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
+ };
+
+ split1: split at 14019000 {
+ compatible = "mediatek,mt8173-disp-split";
+ reg = <0 0x14019000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
+ };
+
+ ufoe at 1401a000 {
+ compatible = "mediatek,mt8173-disp-ufoe";
+ reg = <0 0x1401a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ };
+
+ dsi0: dsi at 1401b000 {
+ compatible = "mediatek,mt8173-dsi";
+ reg = <0 0x1401b000 0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
+ <&mmsys CLK_MM_DSI0_DIGITAL>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
+ dsi1: dsi at 1401c000 {
+ compatible = "mediatek,mt8173-dsi";
+ reg = <0 0x1401c000 0 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
+ <&mmsys CLK_MM_DSI1_DIGITAL>,
+ <&mipi_tx1>;
+ clock-names = "engine", "digital", "hs";
+ phy = <&mipi_tx1>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
+ dpi0: dpi at 1401d000 {
+ compatible = "mediatek,mt8173-dpi";
+ reg = <0 0x1401d000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DPI_PIXEL>,
+ <&mmsys CLK_MM_DPI_ENGINE>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ status = "disabled";
+
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&hdmi0_in>;
+ };
+ };
+ };
+
+ pwm0: pwm at 1401e000 {
+ compatible = "mediatek,mt8173-disp-pwm",
+ "mediatek,mt6595-disp-pwm";
+ reg = <0 0x1401e000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&mmsys CLK_MM_DISP_PWM026M>,
+ <&mmsys CLK_MM_DISP_PWM0MM>;
+ clock-names = "main", "mm";
+ status = "disabled";
+ };
+
+ pwm1: pwm at 1401f000 {
+ compatible = "mediatek,mt8173-disp-pwm",
+ "mediatek,mt6595-disp-pwm";
+ reg = <0 0x1401f000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&mmsys CLK_MM_DISP_PWM126M>,
+ <&mmsys CLK_MM_DISP_PWM1MM>;
+ clock-names = "main", "mm";
+ status = "disabled";
+ };
+
+ mutex: mutex at 14020000 {
+ compatible = "mediatek,mt8173-disp-mutex";
+ reg = <0 0x14020000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ };
+
+ larb0: larb at 14021000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x14021000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ };
+
+ smi_common: smi at 14022000 {
+ compatible = "mediatek,mt8173-smi-common";
+ reg = <0 0x14022000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_COMMON>;
+ clock-names = "apb", "smi";
+ };
+
+ od at 14023000 {
+ compatible = "mediatek,mt8173-disp-od";
+ reg = <0 0x14023000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_OD>;
+ };
+
+ hdmi0: hdmi at 14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+ <&mmsys CLK_MM_HDMI_PLLCK>,
+ <&mmsys CLK_MM_HDMI_AUDIO>,
+ <&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+ assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
+ assigned-clock-parents = <&hdmi_phy>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+ };
+ };
+
+ larb4: larb at 14027000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x14027000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_SMI_LARB4>,
+ <&mmsys CLK_MM_SMI_LARB4>;
+ clock-names = "apb", "smi";
+ };
+
+ imgsys: clock-controller at 15000000 {
+ compatible = "mediatek,mt8173-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb2: larb at 15001000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
+ clocks = <&imgsys CLK_IMG_LARB2_SMI>,
+ <&imgsys CLK_IMG_LARB2_SMI>;
+ clock-names = "apb", "smi";
+ };
+
+ vdecsys: clock-controller at 16000000 {
+ compatible = "mediatek,mt8173-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vcodec_dec: vcodec at 16000000 {
+ compatible = "mediatek,mt8173-vcodec-dec";
+ reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
+ <0 0x16020000 0 0x1000>, /* VDEC_MISC */
+ <0 0x16021000 0 0x800>, /* VDEC_LD */
+ <0 0x16021800 0 0x800>, /* VDEC_TOP */
+ <0 0x16022000 0 0x1000>, /* VDEC_CM */
+ <0 0x16023000 0 0x1000>, /* VDEC_AD */
+ <0 0x16024000 0 0x1000>, /* VDEC_AV */
+ <0 0x16025000 0 0x1000>, /* VDEC_PP */
+ <0 0x16026800 0 0x800>, /* VDEC_HWD */
+ <0 0x16027000 0 0x800>, /* VDEC_HWQ */
+ <0 0x16027800 0 0x800>, /* VDEC_HWB */
+ <0 0x16028400 0 0x400>; /* VDEC_HWG */
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb1>;
+ iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
+ mediatek,vpu = <&vpu>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
+ clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
+ <&topckgen CLK_TOP_UNIVPLL_D2>,
+ <&topckgen CLK_TOP_CCI400_SEL>,
+ <&topckgen CLK_TOP_VDEC_SEL>,
+ <&topckgen CLK_TOP_VCODECPLL>,
+ <&apmixedsys CLK_APMIXED_VENCPLL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>,
+ <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ clock-names = "vcodecpll",
+ "univpll_d2",
+ "clk_cci400_sel",
+ "vdec_sel",
+ "vdecpll",
+ "vencpll",
+ "venc_lt_sel",
+ "vdec_bus_clk_src";
+ };
+
+ larb1: larb at 16010000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
+ clocks = <&vdecsys CLK_VDEC_CKEN>,
+ <&vdecsys CLK_VDEC_LARB_CKEN>;
+ clock-names = "apb", "smi";
+ };
+
+ vencsys: clock-controller at 18000000 {
+ compatible = "mediatek,mt8173-vencsys", "syscon";
+ reg = <0 0x18000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb3: larb at 18001000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x18001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
+ clocks = <&vencsys CLK_VENC_CKE1>,
+ <&vencsys CLK_VENC_CKE0>;
+ clock-names = "apb", "smi";
+ };
+
+ vcodec_enc: vcodec at 18002000 {
+ compatible = "mediatek,mt8173-vcodec-enc";
+ reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
+ <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb3>,
+ <&larb5>;
+ iommus = <&iommu M4U_PORT_VENC_RCPU>,
+ <&iommu M4U_PORT_VENC_REC>,
+ <&iommu M4U_PORT_VENC_BSDMA>,
+ <&iommu M4U_PORT_VENC_SV_COMV>,
+ <&iommu M4U_PORT_VENC_RD_COMV>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA>,
+ <&iommu M4U_PORT_VENC_REF_LUMA>,
+ <&iommu M4U_PORT_VENC_REF_CHROMA>,
+ <&iommu M4U_PORT_VENC_NBM_RDMA>,
+ <&iommu M4U_PORT_VENC_NBM_WDMA>,
+ <&iommu M4U_PORT_VENC_RCPU_SET2>,
+ <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
+ <&iommu M4U_PORT_VENC_BSDMA_SET2>,
+ <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
+ <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ mediatek,vpu = <&vpu>;
+ clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_UNIVPLL1_D2>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "venc_sel_src",
+ "venc_sel",
+ "venc_lt_sel_src",
+ "venc_lt_sel";
+ };
+
+ vencltsys: clock-controller at 19000000 {
+ compatible = "mediatek,mt8173-vencltsys", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb5: larb at 19001000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0 0x19001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
+ clocks = <&vencltsys CLK_VENCLT_CKE1>,
+ <&vencltsys CLK_VENCLT_CKE0>;
+ clock-names = "apb", "smi";
+ };
+ };
+};
+
--
2.11.0.483.g087da7b7c-goog
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