[PATCH 06/10] soc/qbman: Add ARM equivalent for flush_dcache_range()

[Russell King - ARM Linux]

On Wed, Feb 01, 2017 at 01:47:46PM +0100, Arnd Bergmann wrote:
> Ah right, so since there is no interface to map as "device writeback",
> the driver would likely end up with an MMIO register in a
> "normal writeback", with these properties (among others listed there):

It's not about there being no _interface_, there's no support in the
architecture for it.  The use of the "device" memory type does not
allow for any form of cache hints to be specified.

>  * - writes can be repeated (in certain cases) with no side effects
>  * - writes can be merged before accessing the target
>  * - unaligned accesses can be supported
>  * - ordering is not guaranteed without explicit dependencies or barrier
>  *   instructions
>  * - writes may be delayed before they hit the endpoint memory
> 
> I think the ordering is the most critical here, as IIRC the driver
> expects a whole cache line to be written into the MMIO register
> in a single bus cycle specifically when we issue the flush from the
> driver, but we can actually have partial writebacks at any time.

I don't think that's achievable, unless your data bus is as wide as
a cache line (iow, for a 32-byte cache line, your data bus all the
way to the peripheral would need to be 256 bits wide to write the
cache line in a single bus cycle.)

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