[PATCH v2] arm/arm64: KVM: VGIC: limit ITARGETSR bits to number of VCPUs

[Christoffer Dall]

On Wed, Nov 16, 2016 at 05:57:16PM +0000, Andre Przywara wrote:
> The GICv2 spec says in section 4.3.12 that a "CPU targets field bit that
> corresponds to an unimplemented CPU interface is RAZ/WI."
> Currently we allow the guest to write any value in there and it can
> read that back.
> Mask the written value with the proper CPU mask to be spec compliant.
> 
> Signed-off-by: Andre Przywara <andre.przywara at arm.com>

Reviewed-by: Christoffer Dall <christoffer.dall at linaro.org>