[PATCH V4 6/7] iommu/msm: Use writel_relaxed and add a barrier
sricharan at codeaurora.org
Wed May 18 05:33:51 PDT 2016
>> >These comments are completely useless. What is the specific race
>> >that you are protecting against, and why are the implicit barriers
>> >not sufficient here? Please find a better way to document what
>> >is going on.
>> The reason for doing this was, when the tlb maintenance ops are called
>> by io-pgtable functions, it expects that the tlb_range ops is complete
>> only after the tlb_sync callback is called. Previously we were using
>> writel and the sync in that case was dummy. Also previously every register
>> configuration write was done using writel, which was an overkill. So now
>> we do all the writes with writel_relaxed and a barrier in the end. I will
>> change the documentation for this.
>If you need the barrier after the write, it probably was already faulty
>before, because writel only implies a barrier before the store, not
>after. Of course all the barriers likely made the whole process so
>slow that you never hit that race in the end.
ya, it could have worked in this way and i never saw a race issue before this.
The only reason for changing this was to optimise out the additonal barriers
that were happening. I do not see any issue now as well, only that the writes would
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