[linux-sunxi] Problem with Allwinner H3 clocks

[Chen-Yu Tsai]

On Fri, Jan 29, 2016 at 2:25 PM, Hans de Goede <hdegoede at redhat.com> wrote:
> Hi,
>
> On 01/28/2016 08:29 PM, Maxime Ripard wrote:
>>
>> On Thu, Jan 28, 2016 at 05:59:18PM +0100, Jean-Francois Moine wrote:
>
>
> <snip>
>
>>> The A23/A33/H3 (and surely some other SoCs) documentations about
>>> the peripheral/periph/periph0/periph1 PLLs say:
>>>
>>>         Note: The PLL Output should be fixed to 600MHz, it is not
>>>         recommended to vary this value arbitrarily.
>>
>>
>> I don't know if it's worth it at this point. The pll6 seems to work
>> fine at other rates. Have you experienced any breakage when running at
>> another frequency?
>
>
> Hmm, are we actually changing the freq of pll6 on any SoCs? I know we've
> the code to it, but given that it is shared between many pheripherals,
> I assume we end up never changing it. I assume / hope that the clock
> framework protects against reclocking a clock with multiple users ...

No we're not. And none of the children of pll6 have CLK_SET_RATE_PARENT
set, so they won't change pll6. I think the point is pll6 itself _can_
be changed, but that would screw up all the peripherals depending on it.

There's also SATA and USB that might be driven by it.

ChenYu