some question about Set bit 22 in the PL310 (cache controller) AuxCtlr register
vichy.kuo at gmail.com
Wed Mar 11 07:35:35 PDT 2015
2015-03-11 0:31 GMT+08:00 Catalin Marinas <catalin.marinas at arm.com>:
> On Sun, Mar 08, 2015 at 08:31:45PM +0800, vichy wrote:
>> Recently we bumped into the same issue like below path:
>> We have some question about this patch:
>> a. Under what circumstances, there will be memory returned by
>> dma_alloc_coherent and friends mapped as normal, cacheable mappings?
> dma_alloc_coherent() allocating from ZONE_DMA (or ZONE_NORMAL) which is
> already mapped in the kernel linear mapping as Normal Cacheable.
>> b. why "with CMA enabled, it should be safe not to set this bit."
> It's not entirely safe either. I guess the assumption is that CMA
> allocates from highmem which is not mapped in the kernel linear mapping.
> However, to be able to flush the caches for such highmem pages, they
> need to be mapped (kmap_atomic() in __dma_clear_buffer()) but there is a
> small window between dmac_flush_range() and kunmap_atomic() where
> speculative cache line fills can still happen.
> Bit 22 in PL310 AuxCtlr must be set for most (all) uses of the coherent
> DMA API in Linux.
if so, under what circumstance, the Bit22 in PL310 AuxCtlr will be cleared?
thanks your kind help,
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