some question about Set bit 22 in the PL310 (cache controller) AuxCtlr register

[Russell King - ARM Linux]

On Tue, Mar 10, 2015 at 05:11:51PM +0000, Krishna Reddy wrote:
> > > b. why "with CMA enabled, it should be safe not to set this bit."
> > 
> > It's not entirely safe either. I guess the assumption is that CMA allocates from
> > highmem which is not mapped in the kernel linear mapping.
> > However, to be able to flush the caches for such highmem pages, they need
> > to be mapped (kmap_atomic() in __dma_clear_buffer()) but there is a small
> > window between dmac_flush_range() and kunmap_atomic() where
> > speculative cache line fills can still happen.
> 
> Even Low mem CMA pages has similar race window as highmem CMA pages. 
> __free_from_contiguous() in dma-mapping.c maps the CMA Low Mem pages as
>  Cached using __dma_remap().
> During the subsequent allocation of same CMA low mem pages, the window exist between
> __dma_clear_buffer() and __dma_remap() in __alloc_from_contiguous().

Again, something else which needs to be fixed.

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