[PATCH v2 17/20] arm64: atomics: prefetch the destination word for write prior to stxr

[Catalin Marinas]

On Fri, Jul 24, 2015 at 11:42:08AM +0100, Will Deacon wrote:
> The cost of changing a cacheline from shared to exclusive state can be
> significant, especially when this is triggered by an exclusive store,
> since it may result in having to retry the transaction.
> 
> This patch makes use of prfm to prefetch cachelines for write prior to
> ldxr/stxr loops when using the ll/sc atomic routines.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>