[PATCH v3 1/3] clk: mediatek: Fix PLL registers setting flow
sboyd at codeaurora.org
Fri Jul 17 17:47:49 PDT 2015
On 07/10, James Liao wrote:
> Write postdiv and pcw settings at the same time for PLLs if postdiv
> and pcw settings are on the same register.
> This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
> Signed-off-by: James Liao <jamesjj.liao at mediatek.com>
Applied to clk-next
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