[PATCH] arm64: Define HAVE_ARCH_PIO_SIZE and related symbols.
will.deacon at arm.com
Tue Jul 14 10:04:08 PDT 2015
On Tue, Jul 14, 2015 at 05:58:20PM +0100, David Daney wrote:
> On 07/14/2015 09:29 AM, Will Deacon wrote:
> > On Tue, Jul 14, 2015 at 05:12:57PM +0100, David Daney wrote:
> >> Systems based on the Cavium ThunderX processor may have up to 8
> >> independent PCIe root complexes. The I/O space on each bus occupies an
> >> independent physical address window.
> > Hmm, so do you have 64k of I/O space per-bus? That gives 8x256x64k = 128M
> > IIUC, so not sure what your 32MB is for.
> I don't understand where your 256 came from there.
Sorry, sounds like we're mixing up buses and root complexes. Which is it?
> Actually, my current implementation has 1M per bus(which is overkill).
> For 8 buses I need 8M, which fits within the PCI_IO_SIZE...
So there's no problem?
> >> So, in order to be able to map all of these (semi) contiguously, we need
> >> a lot more virtual address space than is supplied by the default values
> >> for all these constants.
> >> The option I chose here was to unconditionally expand the I/O ranges for
> >> all arm64 systems. If you think this breaks existing systems/drivers, I
> >> will have to look for other options.
> > Hmm, but pci_iomap winds up calling __pci_ioport_map, which expands to
> > ioport_map which just does:
> > return PCI_IOBASE + (port & IO_SPACE_LIMIT);
> > so I'm struggling to see what your patch achieves.
> Here is ioport_map (from lib/iomap.c):
> void __iomem *ioport_map(unsigned long port, unsigned int nr)
> if (port > PIO_MASK)
> return NULL;
> return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
We only get this definition if CONFIG_GENERIC_IOMAP=y. Why is that
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