[PATCH V3 06/19] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2

[Jon Hunter]

On 13/07/15 14:41, Peter De Schrijver wrote:
> On Mon, Jul 13, 2015 at 01:39:44PM +0100, Jon Hunter wrote:
>> From: Vince Hsu <vinceh at nvidia.com>
>>
>> Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when
>> the DIS power domain is during up-powergating process but the clamp to this
> 
> I think there is missing 'off' in this sentence?
> 
> ie. ... 'the DIS power domain is off during up-powergating process'
> 
> Also 'un-powergating sequence' would be nicer.

Yes agree. I will re-word that.

Thanks
Jon