[PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow

[Heiko Stübner]

Am Mittwoch, 8. Juli 2015, 16:37:45 schrieb James Liao:
> Write postdiv and pcw settings at the same time for PLLs if postdiv
> and pcw settings are on the same register.
> 
> This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
> 
> Signed-off-by: James Liao <jamesjj.liao at mediatek.com>

Reviewed-by: Heiko Stuebner <heiko at sntech.de>