[PATCH v2 1/9] clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac

[Stephen Boyd]

On 06/18, Heiko Stuebner wrote:
> The dwmac ethernet controller on the rk3288 supports phys connected
> via rgmii and rmii. With rgmii phys it is expected that the mac clock
> is provided externally while with rmii phys the clock can be external
> but also generated from the plls. In the later case it of course needs
> be at 50MHz, which gets set from the dwmac_rk driver.
> As most devices use a rgmii phy it never surfaced so far that the mac
> clk mux, doesn't go up one lever to the pll clock in the rmii case with
> internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag,
> and thus will not set the correct frequency in most cases.
> 
> Fixes: b9e4ba541607 ("clk: rockchip: add clock controller for rk3288")
> Cc: stable at vger.kernel.org
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> ---

Applied to clk-rk3368

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