Programming the boundary between Inner and Outer caches on ARM architecture

[Catalin Marinas]

On Thu, Apr 09, 2015 at 09:45:08PM +0530, Bhaskara rao Budiredla wrote:
> Hi - can someone please provide the register details to configure the
> boundary between Inner and Outer caches? In a three level cache
> system, it is desired to apply Inner cacheable attributes to level 1
> cache and Outer cacheable attributes to level two & level three
> caches.

Who told you that?

-- 
Catalin