[PATCH] arm: fix flush_pfn_alias

[Jungseung Lee]

> >> L1_CACHE_BYTES could be larger than real L1 cache line size.
> >> In that case, flush_pfn_alias function would omit to flush last bytes
> >> as much as L1_CACHE_BYTES - real cache line size.
> >
> >Can you list an example on what CPU this would happen in the
> >patch description? Isn't the L1 cache line size always 32 bytes on ARM?
>

It's 64bytes on A15 and 32bytes on A9.
However, L1_CACHE_BYTES is 64 on ARMv7.

>
> > So fix end address to "to + PAGE_SIZE - 1". The bottom bits of the address
> > is LINELEN. that is ignored by mcrr.
> >
> > Signed-off-by: Jungseung Lee <js07.lee at gmail.com>
>
> Is this needed in stable backports?

Maybe no.

As Russell and Will said, it always would be 32bytes for this codpath.
So that would not make any problem. In my CA9 kernel image, the
function is not included also.

But the code that using L1_CACHE_BYTES should be modified ,
since that is not real cache line size and cause misunderstanding.