[PATCH] arm: fix flush_pfn_alias

[Russell King - ARM Linux]

On Mon, Oct 20, 2014 at 03:39:44PM +0200, Arnd Bergmann wrote:
> On Monday 20 October 2014 21:54:02 Jungseung Lee wrote:
> > L1_CACHE_BYTES could be larger than real L1 cache line size.
> > In that case, flush_pfn_alias function would omit to flush last bytes
> > as much as L1_CACHE_BYTES - real cache line size.
> 
> Can you list an example on what CPU this would happen in the
> patch description? Isn't the L1 cache line size always 32 bytes on ARM?

No, there are 64-byte cache lines in some v7 CPUs.

> Is this needed in stable backports?

The MCRR instruction is deprecated (presumably because, as I discovered
in the early days, it can prevent the system making progress under high
interrupt load), but is only used on ARMv6 CPUs with aliasing cachces -
which have a cache line size of 32.  However, when built alongside ARMv7,
it is possible that L1_CACHE_SIZE could be 64.

The patch seems sane on the face of it.

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