[PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles

Jisheng Zhang jszhang at marvell.com
Thu Jun 12 03:15:03 PDT 2014

Hi Russell,

On Thu, 12 Jun 2014 02:44:23 -0700
Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:

> On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > For all BG2Q SoCs, 2 cycles is the best/correct value
> It would be a good idea to set all these parameters if you need to set
> them at all - in other words, setting arm,dirty-latency as well, as
> that's all part of the timing specification.

Thanks for reviewing this patch. I will check with SoC people to find the correct
dirty-latency value.


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