[PATCH v8 3/4] ata: Add APM X-Gene SoC SATA host controller driver

[Loc Ho]

Hi,

>> In the ISR, the AHCI library code reads the CI register and then
>> performs XOR to determine which commands are completed. Then it goes
>> and processes the completed command(s). I am worry that the process of
>> processing the completed command(s), the upper layer may act on the
>> data before the data arrived at the DDR/cache. In answering your
>> question, yes.
>
> Is this an explicit errata on the hardware?  Have you actually
> observed this or is it just a speculation?
>

This issue has NOT been observed but the design has this issue and
observed from verification. As a mean to ensure that this never occur
from design itself, this is the workaround and only apply to SATA and
SDIO. The SDIO don't need this special flush as discussed in earlier
email.

-Loc