[PATCH v8 3/4] ata: Add APM X-Gene SoC SATA host controller driver

[Loc Ho]

Hi,


>> > As mentioned, the flush requires immediately after reading the CI.
>> > Otherwise, there is still an chance that the command is completed and
>> > the OS notified the upper layer while the data is still in flight. For
>> > the initial version, I will remove the flush (IRQ wrapper) and submit
>> > separate patch.
>>
>> The function is called with ap->lock held.  Nothing can happen
>> inbetween.
>
> Oh, or do you mean that upper layer may get data which hasn't finish
> transferring without the flush?
>

In the ISR, the AHCI library code reads the CI register and then
performs XOR to determine which commands are completed. Then it goes
and processes the completed command(s). I am worry that the process of
processing the completed command(s), the upper layer may act on the
data before the data arrived at the DDR/cache. In answering your
question, yes.

-Loc.