[linux-sunxi] Re: [PATCH v2 3/3] ARM: sun7i: irqchip: Update the documentation

[Arnd Bergmann]

On Thursday 09 January 2014, Carlo Caione wrote:
> In Allwinner A20/A31 SoCs NMI controller is an independent module
> external and in cascade with the GIC. It catches the NMI pin's state
> and generates irq to GIC.
> (therefore NMI is not really not Non-maskable but it is a normal interrupt).
> Here is an ascii-plot of the system (thanks to Maxime and the
> Allwinner engineers for this)
> 
>            +---------+            +-----------+
>            |         +------------+ FIQ       |
>            |   GIC   |            |           |
>            |         +------------+ INT   CPU |
>            +--+---+--+            |           |
>               |   |               |           |
>               |   +------+        |           |
>               |          |        |           |
>  +-----+   +--+--+   +---+---+    |           |
>  | AXP +-+-+ NMI +   | ALARM |    |           |
>  +-----+ | +-----+   +---+---+    +-----------+
>          |               |
>          +---------------+

Ah, cool. That certianly makes sense now. Thanks for the explanation.

	Arnd