[PATCH 1/3] clk: socfpga: Fix integer overflow in clock calculation

[Mike Turquette]

Quoting dinguyen at altera.com (2014-02-19 13:11:10)
> From: Dinh Nguyen <dinguyen at altera.com>
> 
> Use 64-bit integer for calculating clock rate. Also use do_div for the
> 64-bit division.
> 
> Signed-off-by: Graham Moore <grmoore at altera.com>
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: Steffen Trumtrar <s.trumtrar at pengutronix.de>

Changes to the clk driver look good to me.

Regards,
Mike

> ---
>  drivers/clk/socfpga/clk-pll.c |    8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
> index 362004e..834b6e9 100644
> --- a/drivers/clk/socfpga/clk-pll.c
> +++ b/drivers/clk/socfpga/clk-pll.c
> @@ -44,7 +44,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
>                                          unsigned long parent_rate)
>  {
>         struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
> -       unsigned long divf, divq, vco_freq, reg;
> +       unsigned long divf, divq, reg;
> +       unsigned long long vco_freq;
>         unsigned long bypass;
>  
>         reg = readl(socfpgaclk->hw.reg);
> @@ -54,8 +55,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
>  
>         divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
>         divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
> -       vco_freq = parent_rate * (divf + 1);
> -       return vco_freq / (1 + divq);
> +       vco_freq = (unsigned long long)parent_rate * (divf + 1);
> +       do_div(vco_freq, (1 + divq));
> +       return (unsigned long)vco_freq;
>  }
>  
>  static struct clk_ops clk_pll_ops = {
> -- 
> 1.7.9.5
>